Forth v6 Assembler Glossary

This glossary describes the library of words used in assembly language programming within the Forth environment. Assembler mode is switched on using the CODE or >ASSM keywords, and switched off using END.CODE or >FORTH. Please consult the assembly programming manual for instruction in using the Forth assembler.

For help in understanding the notation used in the following function definitions, consult the description of stack symbols, abbreviations and naming conventions.

Software development in Forth (and its in-line assembler) uses the Codeblocks-based Mosaic IDE Plus Integrated Development Environment; this is the same IDE used for software development in C. While Forth programmers will not use the IDE's GNU C (GCC) compiler, the IDE provides a full-featured text editor and customized terminal for rapid code downloads and interactive debugging sessions with the 9S12 (HCS12) processor on the controller board.

+LOOP, ( reg.arg -- )

Terminates a loop structure of the form:

BEGIN,  <code to be iterated>   reg.arg +LOOP, 

where reg.arg must be one of the following:

A,  B,  D,  X,  Y,  S,

On each pass through the loop, the counter register specified by reg.arg is incremented by 1, and the loop continues until the counter register = 0. The backwards branch compiled by this code is limited to -256 bytes.
Pronunciation: “plus-loop-comma”

,+PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-preincrement program counter register PC indexed addressing mode should be used by an instruction opcode. This mode increments the PC register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-preincrement-indexed-p-c"

,+S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-preincrement stack pointer register S indexed addressing mode should be used by an instruction opcode. This mode increments the S register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-preincrement-indexed-s"

,+X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-preincrement index register X indexed addressing mode should be used by an instruction opcode. This mode increments the X register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-preincrement-indexed-x"

,+Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-preincrement index register Y indexed addressing mode should be used by an instruction opcode. This mode increments the Y register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-preincrement-indexed-y"

,-PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-predecrement program counter register PC indexed addressing mode should be used by an instruction opcode. This mode decrements the PC register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-predecrement-indexed-p-c"

,-S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-predecrement stack pointer register S indexed addressing mode should be used by an instruction opcode. This mode decrements the S register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-predecrement-indexed-s"

,-X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-predecrement index register X indexed addressing mode should be used by an instruction opcode. This mode decrements the X register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-predecrement-indexed-x"

,-Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-predecrement index register Y indexed addressing mode should be used by an instruction opcode. This mode decrements the Y register by a specified integer value in the range –8 through –1 or 1 through 8 before indexing occurs.
Pronunciation: "auto-predecrement-indexed-y"

,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset program counter register PC indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. IND,PC is a synonym for this mode.
Pronunciation: "indexed-p-c"

,PC+ ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postincrement program counter register PC indexed addressing mode should be used by an instruction opcode. This mode increments the PC register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postincrement-indexed-p-c"

,PC- ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postdecrement program counter register PC indexed addressing mode should be used by an instruction opcode. This mode decrements the PC register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postdecrement-indexed-p-c"

,PCR ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the program-counter-relative addressing mode should be used by an instruction opcode. The ,PCR mode accepts an argument equal to a destination address, calculates the effective relative offset to it from the PC reference addr (the first byte of the next instruction when the code is being assembled), and compiles an instruction using the IND16,PC indexed addressing mode to reach the specified address. The advantage of this mode is that it is relocatable. Due to restrictions imposed by the HCS12 processor, the ,PCR mode can not be used with the following assembly commands:

MOVW   MOVB   MAXA   MINA   EMAXD   EMIND
MAXM   MINM   EMAXM   EMINM   TBL   ETBL  

These restrictions are enforced by the assembler.
Pronunciation: "p-c-relative"

,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset stack pointer register S indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. IND,S is a synonym for this mode.
Pronunciation: "indexed-s"

,S+ ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postincrement stack pointer register S indexed addressing mode should be used by an instruction opcode. This mode increments the S register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postincrement-indexed-s"

,S- ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postdecrement stack pointer register S indexed addressing mode should be used by an instruction opcode. This mode decrements the S register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postdecrement-indexed-s"

,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset index register X indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. IND,X is a synonym for this mode.
Pronunciation: "indexed-x"

,X+ ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postincrement index register X indexed addressing mode should be used by an instruction opcode. This mode increments the X register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postincrement-indexed-x"

,X- ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postdecrement index register X indexed addressing mode should be used by an instruction opcode. This mode decrements the X register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postdecrement-indexed-x"

,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset index register Y indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. IND,Y is a synonym for this mode.
Pronunciation: "indexed-y"

,Y+ ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postincrement index register Y indexed addressing mode should be used by an instruction opcode. This mode increments the Y register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postincrement-indexed-y"

,Y- ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the auto-postdecrement index register Y indexed addressing mode should be used by an instruction opcode. This mode decrements the Y register by a specified integer value in the range –8 through –1 or 1 through 8 after indexing occurs.
Pronunciation: "auto-postdecrement-indexed-y"

-LOOP, ( reg.arg -- )

Terminates a loop structure of the form:

BEGIN,  <code to be iterated>   reg.arg -LOOP, 

where reg.arg must be one of the following:

A,  B,  D,  X,  Y,  S,

On each pass through the loop, the counter register specified by reg.arg is decremented by 1, and the loop continues until the counter register = 0. The backwards branch compiled by this code is limited to -256 bytes.
Pronunciation: “minus-loop-comma”

>ASSM ( -- )

Enables the compilation of in-line assembly code into a high level Forth definition. Consult the main glossary.
Pronunciation: “to-assembly”

>FORTH ( -- )

Enables the compilation of high level Forth code into an assembly language definition. Consult the main glossary.
Pronunciation: “to-forth”

A, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that accumulator A is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "a-register"

A,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator A offset indexed addressing mode relative to the PC (program counter) register should be used by an instruction opcode. This mode adds the value in A to the contents of PC to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-a-comma-p-c"

A,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator A offset indexed addressing mode relative to the S (stack pointer) register should be used by an instruction opcode. This mode adds the value in A to the contents of S to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-a-comma-s"

A,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator A offset indexed addressing mode relative to the index register X register should be used by an instruction opcode. This mode adds the value in A to the contents of X to form the address of the value to be acted upon by the instruction.
Pronunciation: “indexed-a-comma-x"

A,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator A indirect indexed addressing mode relative to the index register Y register should be used by an instruction opcode. This mode adds the value in A to the contents of Y to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-a-comma-y"

ABA ( -- )

Compiles the opcode sequence for the ABA instruction into the dictionary. When later executed, this code adds the contents of accumulator A and accumulator B, and stores the result in accumulator A.
Pronunciation: "add-b-to-a"

ABX ( -- )

Compiles the opcode sequence for the ABX instruction into the dictionary. When later executed, this code adds the unsigned 8 bit contents of accumulator B to the contents of register X and leaves the result in X.
Pronunciation: "add-b-to-x"

ABY ( -- )

Compiles the opcode sequence for the ABY instruction into the dictionary. When later executed, this code adds the unsigned 8 bit contents of accumulator B to the contents of register Y and leaves the result in Y.
Pronunciation: "add-b-to-y"

ADCA ( [arg]\mode -- )

Compiles the opcode sequence for the ADCA instruction into the dictionary. When later executed, this code adds the carry bit to the sum of the operand (specified by arg and mode) and the contents of accumulator A, and places the result in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "add-with-carry-to-a"

ADCB ( [arg]\mode -- )

Compiles the opcode sequence for the ADCB instruction into the dictionary. When later executed, this code adds the carry bit to the sum of the operand (specified by arg and mode) and the contents of accumulator B, and places the result in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "add-with-carry-to-b"

ADDA ( [arg]\mode -- )

Compiles the opcode sequence for the ADDA instruction into the dictionary. When later executed, this code adds the operand (specified by arg and mode) and the contents of accumulator A, and places the result in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "add-a"

ADDB ( [arg]\mode -- )

Compiles the opcode sequence for the ADDB instruction into the dictionary. When later executed, this code adds the operand (specified by arg and mode) and the contents of accumulator B, and places the result in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "add-b"

ADDD ( [arg]\mode -- )

Compiles the opcode sequence for the ADDD instruction into the dictionary. When later executed, this code adds the operand (specified by arg and mode) and the contents of accumulator D, and places the result in accumulator D. The accumulator-offset modes do not require an arg input.
Pronunciation: "add-d"

AGAIN, ( -- )

Used within a code definition to designate the end of an assembly coded infinite loop. Use as:

BEGIN,    [code to be iterated]
AGAIN, 

The words between BEGIN, and AGAIN, are executed indefinitely. The compiled backwards branch is limited to –128 bytes; use LONG.AGAIN, for longer loops. AGAIN, is equivalent to NEVER UNTIL,
Pronunciation: "again-comma"

ALWAYS ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Indicates an "always true" condition.

ANDA ( [arg]\mode -- )

Compiles the opcode sequence for the ANDA instruction into the dictionary. When later executed, this code performs the logical AND of the operand (specified by arg and mode) and the contents of accumulator A, and places the result in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "and-a"

ANDB ( [arg]\mode -- )

Compiles the opcode sequence for the ANDB instruction into the dictionary. When later executed, this code performs the logical AND of the operand (specified by arg and mode) and the contents of accumulator B, and places the result in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "and-b"

ANDCC ( arg\mode -- | mode must be IMM )

Compiles the opcode sequence for the ANDCC instruction into the dictionary. When later executed, this code performs the logical AND of the operand (specified by immediate data arg and mode IMM) and the contents of the condition code register, and places the result in the condition code register.
Pronunciation: "and-c-c"

ANY.BITS.CLR ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used in conjunction with a single-byte argument (which we'll designate as P) and a bit mask (designated as Q). The condition is true if any bits are clear in the result obtained by performing the logical AND operation P AND Q. This condition code is associated with the test and branch instructions BRSET and BRCLR.
Pronunciation: "any-bits-clear"

ANY.BITS.SET ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used in conjunction with a single-byte argument (which we'll designate as P) and a bit mask (designated as Q). The condition is true if any bits are set in the result obtained by performing the logical AND operation P AND Q. This condition code is associated with the test and branch instructions BRSET and BRCLR.

ASL ( [arg]\mode -- )

Compiles the opcode sequence for the ASL instruction into the dictionary. When later executed, this code causes an arithmetic shift left of the 8-bit operand which is specified by arg and mode. The C (carry) bit in the CCR is loaded from the most significant bit of arg, and 0 is shifted into the least significant bit. The accumulator-offset modes do not require an arg input.
Pronunciation: "arithmetic-shift-left"

ASLA ( -- )

Compiles the opcode sequence for the ASLA instruction into the dictionary. When later executed, this code causes an arithmetic shift left of the contents of accumulator A. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator A, and 0 is shifted into the least significant bit.
Pronunciation: "arithmetic-shift-left-a"

ASLB ( -- )

Compiles the opcode sequence for the ASLB instruction into the dictionary. When later executed, this code causes an arithmetic shift left of the contents of accumulator B. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator B, and 0 is shifted into the least significant bit.
Pronunciation: "arithmetic-shift-left-b"

ASLD ( -- )

Compiles the opcode sequence for the ASLD instruction into the dictionary. When later executed, this code causes an arithmetic shift left of the contents of accumulator D. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator D, and 0 is shifted into the least significant bit.
Pronunciation: "arithmetic-shift-left-d"

ASR ( [arg]\mode -- )

Compiles the opcode sequence for the ASR instruction into the dictionary. When later executed, this code causes an arithmetic shift right of the operand specified by arg and mode. The C (carry) bit in the CCR is loaded from the least significant bit of arg. The most significant bit is held constant. The accumulator-offset modes do not require an arg input.
Pronunciation: "arithmetic-shift-right"

ASRA ( -- )

Compiles the opcode sequence for the ASRA instruction into the dictionary. When later executed, this code causes an arithmetic shift right of the contents of accumulator A. The C (carry) bit in the CCR is loaded from the least significant bit of accumulator A. The most significant bit is held constant.
Pronunciation: "arithmetic-shift-right-a"

ASRB ( -- )

Compiles the opcode sequence for the ASRB instruction into the dictionary. When later executed, this code causes an arithmetic shift right of the contents of accumulator B. The C (carry) bit in the CCR is loaded from the least significant bit of accumulator B. The most significant bit is held constant.
Pronunciation: "arithmetic-shift-right-b"

ASSEMBLER ( -- )

Allows the assembler commands to be found during a dictionary search. Consult the main glossary.

B, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that accumulator B is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "b-register"

B,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator B offset indexed addressing mode relative to the PC (program counter) register should be used by an instruction opcode. This mode adds the value in B to the contents of PC to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-b-comma-p-c"

B,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator B offset indexed addressing mode relative to the S (stack pointer) register should be used by an instruction opcode. This mode adds the value in B to the contents of S to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-b-comma-s"

B,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator B offset indexed addressing mode relative to the index register X register should be used by an instruction opcode. This mode adds the value in B to the contents of X to form the address of the value to be acted upon by the instruction.
Pronunciation: “indexed-b-comma-x"

B,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator B indirect indexed addressing mode relative to the index register Y register should be used by an instruction opcode. This mode adds the value in B to the contents of Y to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-b-comma-y"

BCC ( arg -- )

Compiles the opcode sequence for the BCC instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if C in CCR is clear.
Pronunciation: "branch-if-carry-clear"

BCLR ( byte1\[arg]\mode -- | byte1 = mask )

Compiles the opcode sequence for the BCLR instruction into the dictionary. When later executed, this code clears bits in the operand (specified by arg and mode) which are set in the mask byte1. The accumulator-offset modes do not require an arg input.
Pronunciation: "bit-clear"

BCS ( arg -- )

Compiles the opcode sequence for the BCS instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if C in CCR is set.
Pronunciation: "branch-if-carry-set"

BEGIN, ( -- )

Used within a code definition to designate the beginning of a looping structure. Use as:

BEGIN, . . . . condition.flag UNTIL, 

or

BEGIN, . . . . condition.flag WHILE, . . . . REPEAT, 

or

BEGIN, . . . . AGAIN, 

or

BEGIN,. . . . +LOOP

or

BEGIN,. . . . -LOOP

The words after UNTIL, or REPEAT, or +LOOP or –LOOP are executed after the loop structure terminates. BEGIN, . . . . AGAIN, is an infinite loop. Except for constructs terminated by +LOOP or –LOOP, the branch compiled by this code construct is limited to the range –128 to +127 bytes; if a longer branch is needed, use the LONG.BEGIN, with LONG.UNTIL, or LONG.AGAIN, or LONG.WHILE, and LONG.REPEAT,. The loops terminated by +LOOP or –LOOP can enclose up to 256 bytes of code.
Pronunciation: "begin-comma"

BEQ ( arg -- )

Compiles the opcode sequence for the BEQ instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if Z in CCR is set.
Pronunciation: "branch-if-equal"

BGE ( arg -- )

Compiles the opcode sequence for the BGE instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if either N and V in the CCR are both set, or N and V are both clear. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is greater than or equal to 0.
Pronunciation: "branch-if-greater-than-or-equal-to"

BGND ( -- )

Enters the Background Debug Mode.
Pronunciation: “background”

BGT ( arg -- )

Compiles the opcode sequence for the BGT instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if Z is clear, and either N and V in the CCR are both set, or N and V are both clear. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is greater than 0.
Pronunciation: "branch-if-greater-than"

BHI ( arg -- )

Compiles the opcode sequence for the BHI instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if C and Z in CCR are both clear. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is greater than 0.
Pronunciation: "branch-if-higher"

BHS ( arg -- )

Compiles the opcode sequence for the BHS instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if C in CCR is clear. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is greater than or equal to 0.
Pronunciation: "branch-if-higher-or-same"

BITA ( [arg]\mode -- )

Compiles the opcode sequence for the BITA instruction into the dictionary. When later executed, this code modifies the bits in the condition code register according to the result of performing a logical AND between the operand (specified by arg and mode) and accumulator A. Neither the contents of accumulator A nor the operand are affected. The accumulator-offset modes do not require an arg input.
Pronunciation: "bit-test-a"

BITB ( [arg]\mode -- )

Compiles the opcode sequence for the BITB instruction into the dictionary. When later executed, this code modifies the bits in the condition code register according to the result of performing a logical AND between the operand (specified by arg and mode) and accumulator B. Neither the contents of accumulator B nor the operand are affected. The accumulator-offset modes do not require an arg input.
Pronunciation: "bit-test-b"

BLE ( arg -- )

Compiles the opcode sequence for the BLE instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if Z is set, or N is set and V is clear, or N is clear and V is set in the CCR. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is less than or equal to 0.
Pronunciation: "branch-if-less-than-or-equal-to"

BLO ( arg -- )

Compiles the opcode sequence for the BLO instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if C in CCR is set. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is less than 0.
Pronunciation: "branch-if-lower or same"

BLS ( arg -- )

Compiles the opcode sequence for the BLS instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if either C or Z in CCR is set. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is less than or equal to 0.
Pronunciation: "branch-if-lower-or-same"

BLT ( arg -- )

Compiles the opcode sequence for the BLT instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if either N is set and V is clear in the CCR, or N is clear and V is set. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is less than 0.
Pronunciation: "branch-if-less-than"

BMI ( arg -- )

Compiles the opcode sequence for the BMI instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if N in CCR is set.
Pronunciation: "branch-if-minus"

BNE ( arg -- )

Compiles the opcode sequence for the BNE instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if Z in CCR is clear.
Pronunciation: "branch-if-not-equal"

BPL ( arg -- )

Compiles the opcode sequence for the BPL instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if N in CCR is clear.
Pronunciation: "branch-if-plus"

BRA ( arg -- )

Compiles the opcode sequence for the BRA instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes an unconditional branch to the address equal to PC + arg + 2.
Pronunciation: "branch-always"

BRCLR ( byte1\byte2\[arg]\mode -- | byte1=offset, byte2 =mask )

Compiles the opcode sequence for the BRCLR instruction into the dictionary. When later executed, this code causes a branch to an address if the bits set in the mask byte2 are clear in the operand specified by arg and mode2. The address branched to is equal to:

PC + (number.of.bytes.in.instruction) + byte1 

Indexed indirect modes are not allowed with this instruction. The accumulator-offset modes do not require an arg input.
Pronunciation: "branch-if-bits-clear"

BRN ( arg -- )

Compiles the opcode sequence for the BRN instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code acts as a two byte NOP instruction.
Pronunciation: "branch-never"

BRSET ( byte1\byte2\[arg]\mode -- | byte1=offset, byte2=mask )

Compiles the opcode sequence for the BRSET instruction into the dictionary. When later executed, this code causes a branch to an address if the bits set in the mask byte2 are also set in the operand specified by arg and mode2. The address branched to is equal to:

PC + (number.of.bytes.in.instruction) + byte1 

Indexed indirect modes are not allowed with this instruction. The accumulator-offset modes do not require an arg input.
Pronunciation: "branch-if-bits-set"

BSET ( byte1\[arg]\mode -- | byte1 = mask )

Compiles the opcode sequence for the BSET instruction into the dictionary. When later executed, this code sets bits in the operand (specified by arg and mode) which are set in the mask byte1. The accumulator-offset modes do not require an arg input.
Pronunciation: "bit-set"

BSR ( arg -- )

Compiles the opcode sequence for the BSR instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code causes the PC to be incremented by 2 and pushed onto the return stack, and then branches to the address equal to PC + arg.
Pronunciation: "branch-to-subroutine"

BVC ( arg -- )

Compiles the opcode sequence for the BVC instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if V in CCR is clear.
Pronunciation: "branch-if-overflow-clear"

BVS ( arg -- )

Compiles the opcode sequence for the BVS instruction into the dictionary; the arg is an 8-bit signed relative offset (-128 ≤ arg ≤ 127). When later executed, this code executes a branch to the address equal to PC + arg + 2, if V in CCR is set.
Pronunciation: "branch-if-overflow-set"

CALL ( <name> -- )

Compiles a page-smart call to subroutine <name>. Typically used to invoke a Forth function from within an assembly-coded definition. Consult the main glossary.

CALL, ( [page]\[arg]\mode -- )

Compiles the opcode sequence for the CALL instruction into the dictionary. When later executed, this code increments PC properly and pushes it and the page (PPAGE contents) onto the return stack. Program control is then transferred to the effective address specified by arg and mode. The page input parameter is not present in the indexed indirect modes. The accumulator-offset modes do not require an arg input. Routines called using this opcode are typically terminated using RTC. For routines that are terminated with an RTS instruction, use the JSR calling opcode.
Pronunciation: "call-subroutine"

CBA ( -- )

Compiles the opcode sequence for the CBA instruction into the dictionary. When later executed, this code modifies the bits in the condition code register according to the comparison A - B. The contents of accumulators A and B are not affected.
Pronunciation: "compare-b-to-a"

CC ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. The condition is true when the carry flag in the condition code register is 0. Note: if you wish to use the hex number CC within an assembly definition, type it as 0CC or 0xCC to avoid confusion with this condition code.
Pronunciation: "carry-clear"

CCR, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that the condition code register CC is to be used by an opcode. This register specifier can be used with EXG, TFR, and SEX opcodes.
Pronunciation: "c-c-register"

CLC ( -- )

Compiles the opcode sequence for the CLC instruction into the dictionary. When later executed, this code clears the C (carry) bit in the condition code register.
Pronunciation: "clear-carry"

CLI ( -- )

Compiles the opcode sequence for the CLI instruction into the dictionary. When later executed, this code clears the I (global interrupt enable) bit in the condition code register. Maskable interrupts are enabled when the I bit is clear, so this instruction enables interrupts at runtime.
Pronunciation: "clear-interrupt-mask"

CLR ( [arg]\mode -- )

Compiles the opcode sequence for the CLR instruction into the dictionary. When later executed, this code clears the contents of the operand specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "clear"

CLRA ( -- )

Compiles the opcode sequence for the CLRA instruction into the dictionary. When later executed, this code clears the contents of accumulator A.
Pronunciation: "clear-a"

CLRB ( -- )

Compiles the opcode sequence for the CLRB instruction into the dictionary. When later executed, this code clears the contents of accumulator B.
Pronunciation: "clear-b"

CLV ( -- )

Compiles the opcode sequence for the CLV instruction into the dictionary. When later executed, this code clears the V bit (the 2s complement overflow bit) in the CCR.
Pronunciation: "clear-overflow-bit"

CMPA ( [arg]\mode -- )

Compiles the opcode sequence for the CMPA instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator A and sets the condition code register bits accordingly. The operand and accumulator A are unaffected. The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-a"

CMPB ( [arg]\mode -- )

Compiles the opcode sequence for the CMPB instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator B and sets the condition code register bits accordingly. The operand and accumulator B are unaffected. The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-b"

CODE ( <name> -- )

Starts an assembly coded definition. Consult the main glossary.

COM ( [arg]\mode -- )

Compiles the opcode sequence for the COM instruction into the dictionary. When later executed, this code replaces the operand specified by arg and mode with its ones complement (which is formed by complementing the state of each bit). The accumulator-offset modes do not require an arg input.
Pronunciation: "complement"

COMA ( -- )

Compiles the opcode sequence for the COMA instruction into the dictionary. When later executed, this code replaces the contents of accumulator A with its ones complement (which is formed by complementing the state of each bit).
Pronunciation: "complement-a"

COMB ( -- )

Compiles the opcode sequence for the COMB instruction into the dictionary. When later executed, this code replaces the contents of accumulator B with its ones complement (which is formed by complementing the state of each bit).
Pronunciation: "complement-b"

CPD ( [arg]\mode -- )

Compiles the opcode sequence for the CPD instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator D and sets the condition code register bits accordingly. The operand and accumulator D are unaffected. The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-d"

CPS ( [arg]\mode -- )

Compiles the opcode sequence for the CPS instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of the stack pointer S and sets the condition code register bits accordingly. The operand and stack pointer S are unaffected (unless the mode specifies that S be incremented or decremented). The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-s"

CPX ( [arg]\mode -- )

Compiles the opcode sequence for the CPX instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator X and sets the condition code register bits accordingly. The operand and accumulator X are unaffected (unless the mode specifies that X be incremented or decremented). The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-x"

CPY ( [arg]\mode -- )

Compiles the opcode sequence for the CPY instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator Y and sets the condition code register bits accordingly. The operand and accumulator Y are unaffected (unless the mode specifies that Y be incremented or decremented). The accumulator-offset modes do not require an arg input.
Pronunciation: "compare-y"

CS ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. The condition is true when the carry flag in the condition code register is 1.
Pronunciation: "carry-set"

D, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that accumulator D is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "d-register"

D,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D offset indexed addressing mode relative to the PC (program counter) register should be used by an instruction opcode. This mode adds the value in D to the contents of PC to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-d-comma-p-c"

D,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D offset indexed addressing mode relative to the S (stack pointer) register should be used by an instruction opcode. This mode adds the value in D to the contents of S to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-d-comma-s"

D,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D offset indexed addressing mode relative to the index register X register should be used by an instruction opcode. This mode adds the value in D to the contents of X to form the address of the value to be acted upon by the instruction.
Pronunciation: “indexed-d-comma-x"

D,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D indirect indexed addressing mode relative to the index register Y register should be used by an instruction opcode. This mode adds the value in D to the contents of Y to form the address of the value to be acted upon by the instruction.
Pronunciation: "indexed-d-comma-y"

DAA ( -- )

Compiles the opcode sequence for the DAA instruction into the dictionary. When later executed, this code decimal adjusts the contents of accumulator A to facilitate binary-coded-decimal calculations. For a detailed description of operation, consult the DAA entry in the Motorola HC12 manual.
Pronunciation: "decimal-adjust-a"

DBEQ ( arg\reg.arg -- )

Compiles the opcode sequence for the DBEQ instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code decrements the specified register and, if Z in CCR is set, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "decrement-and-branch-if-equal"

DBNE ( arg\reg.arg -- )

Compiles the opcode sequence for the DBNE instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code decrements the specified register and, if Z in CCR is clear, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "decrement-and-branch-if-not-equal"

DEC ( [arg]\mode -- )

Compiles the opcode sequence for the DEC instruction into the dictionary. When later executed, this code subtracts one from the operand specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "decrement"

DECA ( -- )

Compiles the opcode sequence for the DECA instruction into the dictionary. When later executed, this code subtracts one from the contents of accumulator A.
Pronunciation: "decrement-a"

DECB ( -- )

Compiles the opcode sequence for the DECB instruction into the dictionary. When later executed, this code subtracts one from the contents of accumulator B.
Pronunciation: "decrement-b"

DES ( -- )

Compiles the opcode sequence for the DES instruction into the dictionary. When later executed, this code subtracts one from the contents of the S register which is the return stack pointer.
Pronunciation: "decrement-s"

DEX ( -- )

Compiles the opcode sequence for the DEX instruction into the dictionary. When later executed, this code subtracts one from the contents of the index register X.
Pronunciation: "decrement-x"

DEY ( -- )

Compiles the opcode sequence for the DEY instruction into the dictionary. When later executed, this code subtracts one from the contents of the index register Y.
Pronunciation: "decrement-y"

DIR ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the direct addressing mode should be used by an instruction opcode.
Pronunciation: "direct"

EDIV ( -- )

Compiles the opcode sequence for the EDIV instruction into the dictionary. When later executed, this code performs an extended unsigned 32-bit by 16-bit division, with Y:D as the numerator and X as the denominator. The quotient is returned in Y, and the remainder is returned in D. If X = 0, Y and D do not change, but the N and Z bits of the CCR are undefined.
Pronunciation: “extended-divide”

EDIVS ( -- )

Compiles the opcode sequence for the EDIVS instruction into the dictionary. When later executed, this code performs an extended signed 32-bit by 16-bit division, with Y:D as the numerator and X as the denominator. The quotient is returned in Y, and the remainder is returned in D. If X = 0, Y and D do not change, but the N and Z bits of the CCR are undefined.
Pronunciation: “extended-divide-signed”

ELSE, ( -- )

ELSE, is used in assembly coded routines to mark the beginning of the "else portion" of a conditional structure. Use as:

condition IF,    . . . .
ELSE,    . . . .
ENDIF,  ( or THEN,) 

When executed, ELSE, causes a branch instruction to be compiled into the dictionary and resolves IF,'s branch. When the compiled code is later executed, the code between ELSE, and ENDIF, is executed if the condition is not met. The branches compiled by this code are limited to the range –128 to +127 bytes; if a longer branch is needed, use the LONG.IF, …LONG.ELSE,… LONG.ENDIF, construction.
Pronunciation: "else-comma"

EMACS ( arg16\mode -- | mode must be EXT )

Compiles the opcode sequence for the EMACS instruction into the dictionary. When later executed, this code performs an extended signed multiply and accumulate. The X and Y registers each point to a 16-bit multiplicand, which are multiplied to form a 32-bit intermediate result, and this is added to the 32-bit contents pointed to by the arg16 address.
Pronunciation: “extended-multiply-and-accumulate”

EMAXD ( [arg]\mode -- )

Compiles the opcode sequence for the EMAXD instruction into the dictionary. When later executed, this code performs a 16-bit unsigned “max” operation. The code places into the D register the larger of the unsigned 16 bits referenced by the input arguments, or the unsigned contents of D. The accumulator-offset modes do not require an arg input.
Pronunciation: “extended-max-d”

EMAXM ( [arg]\mode -- )

Compiles the opcode sequence for the EMAXM instruction into the dictionary. When later executed, this code performs a 16-bit unsigned “max” operation. The code places into the location referenced by the input arguments the larger of the unsigned 16 bits referenced by the input arguments, or the unsigned contents of D. The accumulator-offset modes do not require an arg input.
Pronunciation: “extended-max-m”

EMIND ( [arg]\mode -- )

Compiles the opcode sequence for the EMIND instruction into the dictionary. When later executed, this code performs a 16-bit unsigned “min” operation. The code places into the D register the smaller of the unsigned 16 bits referenced by the input arguments, or the unsigned contents of D. The accumulator-offset modes do not require an arg input.
Pronunciation: “extended-min-d”

EMINM ( [arg]\mode -- )

Compiles the opcode sequence for the EMINM instruction into the dictionary. When later executed, this code performs a 16-bit unsigned “min” operation. The code places into the location referenced by the input arguments the smaller of the unsigned 16 bits referenced by the input arguments, or the unsigned contents of D. The accumulator-offset modes do not require an arg input.
Pronunciation: “extended-min-m”

EMUL ( -- )

Compiles the opcode sequence for the EMUL instruction into the dictionary. When later executed, this code performs an extended unsigned 16-bit by 16-bit multiplication of the contents of D times the contents of Y, with the 32-bit result returned in Y:D.
Pronunciation: “extended-multiply”

EMULS ( -- )

Compiles the opcode sequence for the EMULS instruction into the dictionary. When later executed, this code performs an extended signed 16-bit by 16-bit multiplication of the contents of D times the contents of Y, with the 32-bit result returned in Y:D.
Pronunciation: “extended-multiply-signed”

END-CODE ( sys -- | balances CODE )

Ends an assembly coded definition. A synonym for END.CODE. Consult the main glossary.

END.CODE ( sys -- | balances CODE )

Ends an assembly coded definition. Consult the main glossary.

ENDIF, ( -- )

ENDIF, is used in assembly coded routines to mark the end of a conditional IF, structure. ENDIF, and THEN, are synonyms. Use as:

condition IF,    . . . .
ELSE,    . . . .
ENDIF, 

When executed, ENDIF, resolves the branch instructions used in the conditional structure. When the code compiled by the control structure is executed, the code between IF, and ELSE, is executed if the condition is true, and then control passes to the code following ENDIF,. If the condition is false, the code between ELSE, and ENDIF, is executed, and execution continues with the code following ENDIF,. An alternate form is

condition IF, . . . . ENDIF, 

When the code compiled by this control structure is executed, the code between IF, and ENDIF, is executed if the condition is true, and is not executed if the condition is false. The branch compiled by this code is limited to the range –128 to +127 bytes; if a longer branch is needed, use the LONG.IF, …LONG.ELSE,… LONG.ENDIF, construction.
Pronunciation: "end-if-comma"

EORA ( [arg]\mode -- )

Compiles the opcode sequence for the EORA instruction into the dictionary. When later executed, this code performs a logical exclusive or between the contents of accumulator A and the operand specified by arg and mode. The result is stored in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "exclusive-or-a"

EORB ( [arg]\mode -- )

Compiles the opcode sequence for the EORB instruction into the dictionary. When later executed, this code performs a logical exclusive or between the contents of accumulator B and the operand specified by arg and mode. The result is stored in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "exclusive-or-b"

EQ ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P = Q. Alternate interpretation: Condition is true if the Z bit in the condition code register is set.
Pronunciation: "equal"

ETBL ( [arg]\mode -- )

Compiles the opcode sequence for the ETBL instruction into the dictionary. When later executed, this code performs an extended table lookup and interpolate operation. The input parameters specify an index register that in turn points into a table of (x,y) pairs. Any indexed addressing mode, except indirect modes or 9- and 16-bit offset modes can be used. The B register must be pre-loaded with a binary fraction (radix point to the left of the most significant bit in B), and this routine interpolates between the pointed to (x,y) pair and the succeeding (x,y) pair in the table based on the specified fraction. The interpolated Y value is returnd in D. The accumulator-offset modes do not require an arg input.
Pronunciation: “extended-table-lookup”

EXG ( reg.arg1\reg.arg2 -- | reg.arg1 = source register, reg.arg2 = destination register )

Compiles the opcode sequence for the EXG instruction into the dictionary. When later executed, this code exchanges the contents of the specified registers. The reg.arg parameters can be any of the following:

A,   B,  CCR,  D,   X,   Y,    S,

Note: if the destination reg.arg2 is B, or CCR, then the msbyte of B or CCR is assumed to be 0xFF. In all other cases (including if the source reg.arg1 is B, or CCR,), the msbyte of an 8bit register is assumed to be 00.
Pronunciation: “exchange-registers”

EXT ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the extended addressing mode should be used by an instruction opcode.
Pronunciation: "extended"

FDIV ( -- )

Compiles the opcode sequence for the FDIV instruction into the dictionary. When later executed, this code performs an unsigned fractional divide of the 16-bit numerator in accumulator D by the 16-bit denominator in the index register X. The quotient is stored in index register X and the remainder is stored in accumulator D.
Pronunciation: "fractional-divide"

GE ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P ≥ Q using signed math. Alternate interpretation: Condition is true if the N and V bits in the condition code register are either both set or both clear.
Pronunciation: "greater-than-or-equal-to"

GT ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P > Q using signed math. Alternate interpretation: Condition is true if the Z bit is clear, and the N and V bits are either both set or both clear in the condition code register.
Pronunciation: "greater-than"

HI ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P > Q using unsigned math. Alternate interpretation: Condition is true if C and Z in the condition code register are zero.
Pronunciation: "higher"

HS ( -- condition )

Within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P ≥ Q using unsigned math. Alternate interpretation: Condition is true if the C (carry) bit in the condition code register is clear.
Pronunciation: "higher-or-same"

IBEQ ( arg\reg.arg -- )

Compiles the opcode sequence for the IBEQ instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code increments the specified register and, if Z in CCR is set, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "increment-and-branch-if-equal"

IBNE ( arg\reg.arg -- )

Compiles the opcode sequence for the IBNE instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code increments the specified register and, if Z in CCR is clear, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "increment-and-branch-if-not-equal"

IDIV ( -- )

Compiles the opcode sequence for the IDIV instruction into the dictionary. When later executed, this code performs an unsigned integer divide of the 16-bit numerator in accumulator D by the 16-bit denominator in the index register X. The quotient is stored in index register X and the remainder is stored in accumulator D.
Pronunciation: "integer-divide"

IDIVS ( -- )

Compiles the opcode sequence for the IDIVS instruction into the dictionary. When later executed, this code performs a signed integer divide of the 16-bit numerator in accumulator D by the 16-bit denominator in the index register X. The quotient is stored in index register X and the remainder is stored in accumulator D.
Pronunciation: "integer-divide-signed"

IF, ( condition -- )

IF, is used in assembly coded routines to mark the start of a conditional structure. Use as:

condition IF,    . . . .
ELSE,    . . . .
ENDIF,   ( or THEN,) 

or

condition IF,    . . . .
ENDIF,   ( or THEN,) 

When the branch compiled by IF, is executed, the code following IF, is executed if the condition is met, otherwise control is transferred to the code following ELSE, or ENDIF,. (THEN, and ENDIF, are synonyms). The branch compiled by this code is limited to the range –128 to +127 bytes; if a longer branch is needed, use the LONG.IF, …LONG.ELSE,… LONG.ENDIF, construction.
Pronunciation: "if-comma"

IMM ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the immediate addressing mode should be used by an instruction opcode.
Pronunciation: "immediate"

INC ( [arg]\mode -- )

Compiles the opcode sequence for the INC instruction into the dictionary. When later executed, this code adds one to the operand specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "increment"

INCA ( -- )

Compiles the opcode sequence for the INCA instruction into the dictionary. When later executed, this code adds one to the contents of accumulator A.
Pronunciation: "increment-a"

INCB ( -- )

Compiles the opcode sequence for the INCB instruction into the dictionary. When later executed, this code adds one to the contents of accumulator B.
Pronunciation: "increment-b"

IND,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset program counter register PC indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. ,PC is a synonym for this mode.
Pronunciation: "indexed-p-c"

IND,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset stack pointer register S indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. ,S is a synonym for this mode.
Pronunciation: "indexed-s"

IND,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset index register X indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. ,X is a synonym for this mode.
Pronunciation: "indexed-x"

IND,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the optimizing constant offset index register Y indexed addressing mode should be used by an instruction opcode. The assembler selects the optimum offset size of 5-bit (IDX) or 9-bit (IDX1) or 16-bit (IDX2) offset as required. This minimizes code space and execution time. ,Y is a synonym for this mode.
Pronunciation: "indexed-y"

IND16,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant offset program counter register PC indexed addressing mode should be used by an instruction opcode.
Pronunciation: "indexed-sixteen-p-c"

IND16,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant offset stack pointer register S indexed addressing mode should be used by an instruction opcode.
Pronunciation: "indexed-sixteen-s"

IND16,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant offset index register X indexed addressing mode should be used by an instruction opcode.
Pronunciation: "indexed-sixteen-x"

IND16,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit index register Y indexed addressing mode should be used by an instruction opcode.
Pronunciation: "indexed-sixteen-y"

IND5,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 5-bit constant offset program counter register PC indexed addressing mode should be used by an instruction opcode. Offsets in the range of –16 through +15 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-five-p-c"

IND5,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 5-bit constant offset stack pointer register S indexed addressing mode should be used by an instruction opcode. Offsets in the range of –16 through +15 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-five-s"

IND5,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 5-bit constant offset index register X indexed addressing mode should be used by an instruction opcode. Offsets in the range of –16 through +15 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-five-x"

IND5,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 5-bit index register Y indexed addressing mode should be used by an instruction opcode. Offsets in the range of –16 through +15 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-five-y"

IND9,PC ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 9-bit constant offset program counter register PC indexed addressing mode should be used by an instruction opcode. Offsets in the range of –256 through +255 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-nine-p-c"

IND9,S ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 9-bit constant offset stack pointer register S indexed addressing mode should be used by an instruction opcode. Offsets in the range of –256 through +255 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-nine-s"

IND9,X ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 9-bit constant offset index register X indexed addressing mode should be used by an instruction opcode. Offsets in the range of –256 through +255 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-nine-x"

IND9,Y ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 9-bit index register Y indexed addressing mode should be used by an instruction opcode. Offsets in the range of –256 through +255 from the value of the base index register are supported by this mode.
Pronunciation: "indexed-nine-y"

INS ( -- )

Compiles the opcode sequence for the INS instruction into the dictionary. When later executed, this code adds one to the S register which is the return stack pointer.
Pronunciation: "increment-s"

INX ( -- )

Compiles the opcode sequence for the INX instruction into the dictionary. When later executed, this code adds one to index register X.
Pronunciation: "increment-x"

INY ( -- )

Compiles the opcode sequence for the INY instruction into the dictionary. When later executed, this code adds one to index register Y.
Pronunciation: "increment-y"

JMP ( [arg]\mode -- )

Compiles the opcode sequence for the JMP instruction into the dictionary. When later executed, this code transfers control to the instruction stored at the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "jump"

JSR ( [arg]\mode -- )

Compiles the opcode sequence for the JSR instruction into the dictionary. When later executed, this code increments PC properly and pushes it onto the return stack. Program control is then transferred to the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input. Routines called with a JSR are typically terminated using RTS.
Pronunciation: "jump-to-subroutine"

LBCC ( arg -- )

Compiles the opcode sequence for the LBCC instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if C in CCR is clear.
Pronunciation: "long-branch-if-carry-clear"

LBCS ( arg -- )

Compiles the opcode sequence for the LBCS instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if C in CCR is set.
Pronunciation: "long-branch-if-carry-set"

LBEQ ( arg -- )

Compiles the opcode sequence for the LBEQ instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if Z in CCR is set.
Pronunciation: "long-branch-if-equal"

LBGE ( arg -- )

Compiles the opcode sequence for the LBGE instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if either N and V in the CCR are both set, or N and V are both clear. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is greater than or equal to 0.
Pronunciation: "long-branch-if-greater-than-or-equal-to"

LBGT ( arg -- )

Compiles the opcode sequence for the LBGT instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if Z is clear, and either N and V in the CCR are both set, or N and V are both clear. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is greater than 0.
Pronunciation: "long-branch-if-greater-than"

LBHI ( arg -- )

Compiles the opcode sequence for the LBHI instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if C and Z in CCR are both clear. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is greater than 0.
Pronunciation: "long-branch-if-higher"

LBHS ( arg -- )

Compiles the opcode sequence for the LBHS instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if C in CCR is clear. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is greater than or equal to 0.
Pronunciation: "long-branch-if-higher-or-same"

LBLE ( arg -- )

Compiles the opcode sequence for the LBLE instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if Z is set, or N is set and V is clear, or N is clear and V is set in the CCR. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is less than or equal to 0.
Pronunciation: "long-branch-if-less-than-or-equal-to"

LBLO ( arg -- )

Compiles the opcode sequence for the LBLO instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if C in CCR is set. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is less than 0.
Pronunciation: "long-branch-if-lower or same"

LBLS ( arg -- )

Compiles the opcode sequence for the LBLS instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if either C or Z in CCR is set. Typically used after a subtraction or comparison of unsigned numbers, causes a branch if the result is less than or equal to 0.
Pronunciation: "long-branch-if-lower-or-same"

LBLT ( arg -- )

Compiles the opcode sequence for the LBLT instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if either N is set and V is clear in the CCR, or N is clear and V is set. Typically used after a subtraction or comparison of signed numbers, causes a branch if the result is less than 0.
Pronunciation: "long-branch-if-less-than"

LBMI ( arg -- )

Compiles the opcode sequence for the LBMI instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if N in CCR is set.
Pronunciation: "long-branch-if-minus"

LBNE ( arg -- )

Compiles the opcode sequence for the LBNE instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if Z in CCR is clear.
Pronunciation: "long-branch-if-not-equal"

LBPL ( arg -- )

Compiles the opcode sequence for the LBPL instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if N in CCR is clear.
Pronunciation: "long-branch-if-plus"

LBRA ( arg -- )

Compiles the opcode sequence for the LBRA instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes an unconditional branch to the address equal to PC + arg + 4.
Pronunciation: "long-branch-always"

LBRN ( arg -- )

Compiles the opcode sequence for the LBRN instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code acts as a four byte NOP instruction.
Pronunciation: "long-branch-never"

LBVC ( arg -- )

Compiles the opcode sequence for the LBVC instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if V in CCR is clear.
Pronunciation: "long-branch-if-overflow-clear"

LBVS ( arg -- )

Compiles the opcode sequence for the LBVS instruction into the dictionary; the arg is a 16-bit signed relative offset (-32,768 ≤ arg ≤ 32,767). When later executed, this code executes a branch to the address equal to PC + arg + 4, if V in CCR is set.
Pronunciation: "long-branch-if-overflow-set"

LDAA ( [arg]\mode -- )

Compiles the opcode sequence for the LDAA instruction into the dictionary. When later executed, this code loads the operand specified by arg and mode into accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-accumulator-a"

LDAB ( [arg]\mode -- )

Compiles the opcode sequence for the LDAB instruction into the dictionary. When later executed, this code loads the operand specified by arg and mode into accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-accumulator-b"

LDD ( [arg]\mode -- )

Compiles the opcode sequence for the LDD instruction into the dictionary. When later executed, this code loads the operand specified by arg and mode into accumulator D. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-d"

LDS ( [arg]\mode -- )

Compiles the opcode sequence for the LDS instruction into the dictionary. When later executed, this code loads the operand specified by arg and mode into the S register which is the return stack pointer. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-s"

LDX ( [arg]\mode -- )

Compiles the opcode sequence for the LDX instruction into the dictionary. When later executed, this code loads the contents of the operand specified by arg and mode into index register X. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-x"

LDY ( [arg]\mode -- )

Compiles the opcode sequence for the LDY instruction into the dictionary. When later executed, this code loads the contents of the operand specified by arg and mode into index register Y. The accumulator-offset modes do not require an arg input.
Pronunciation: "load-y"

LE ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P ≤ Q using signed math. Alternate interpretation: Condition is true if the Z bit is set, or the N bit is set and V bit is clear, or the N bit is clear and the V bit is set in the condition code register.
Pronunciation: "less-than-or-equal-to"

LEAS ( [arg]\mode -- )

Compiles the opcode sequence for the LEAS instruction into the dictionary. When later executed, this code loads the stack pointer register S with the effective address specified by the input parameters. The condition code register is not affected by this instruction. The accumulator-offset modes do not require an arg input. Note: When used with an auto-pre-increment-S or auto-pre-decrement-S mode, the increment/decrement occurs before the S register is loaded. Auto-post-increment and auto-post-decrement modes do not change the value of S that is loaded.
Pronunciation: "load-effective-address-to-s"

LEAX ( [arg]\mode -- )

Compiles the opcode sequence for the LEAX instruction into the dictionary. When later executed, this code loads the index register X with the effective address specified by the input parameters. The condition code register is not affected by this instruction. The accumulator-offset modes do not require an arg input. Note: When used with an auto-pre-increment-X or auto-pre-decrement-X mode, the increment/decrement occurs before the X register is loaded. Auto-post-increment and auto-post-decrement modes do not change the value of X that is loaded.
Pronunciation: "load-effective-address-to-x"

LEAY ( [arg]\mode -- )

Compiles the opcode sequence for the LEAY instruction into the dictionary. When later executed, this code loads the stack pointer register Y with the effective address specified by the input parameters. The condition code register is not affected by this instruction. The accumulator-offset modes do not require an arg input. Note: When used with an auto-pre-increment-Y or auto-pre-decrement-Y mode, the increment/decrement occurs before the Y register is loaded. Auto-post-increment and auto-post-decrement modes do not change the value of Y that is loaded.
Pronunciation: "load-effective-address-to-y"

LO ( -- condition )

Used inside a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P < Q using unsigned math. Alternate interpretation: Condition is true if the C (carry) bit in the condition code register is set.
Pronunciation: "lower"

LONG.AGAIN, ( -- )

Used within a code definition to designate the end of an assembly coded long infinite loop. Use as:

LONG.BEGIN, [code to be iterated]
LONG.AGAIN, 

The words between BEGIN, and AGAIN, are executed indefinitely. This code compiles a long branch instruction, allowing the loop to span any number of code bytes on a single page. AGAIN, is equivalent to NEVER LONG.UNTIL,
Pronunciation: "long-again-comma"

LONG.BEGIN, ( -- )

Used within a code definition to designate the beginning of a long looping structure. Use as:

LONG.BEGIN, . . . . condition.flag LONG.UNTIL, 

or

LONG.BEGIN, . . . . condition.flag LONG.WHILE, . . . . LONG.REPEAT, 

or

LONG.BEGIN, . . . . LONG.AGAIN, 

The words after LONG.UNTIL, or LONG.REPEAT, are executed after the loop structure terminates. LONG.BEGIN, . . . . LONG.AGAIN, is an infinite loop. This code compiles a long branch instruction, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-begin-comma"

LONG.ELSE, ( -- )

Used in assembly coded routines to mark the beginning of the "else portion" of a long conditional structure. Use as:

condition LONG.IF,    . . . .
LONG.ELSE,    . . . .
LONG.ENDIF,  ( or LONG.THEN,) 

When executed, LONG.ELSE, causes a branch instruction to be compiled into the dictionary and resolves LONG.IF,'s branch. When the compiled code is later executed, the code between LONG.ELSE, and LONG.ENDIF, is executed if the condition is not met. This code construct compiles long branch instructions, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-else-comma"

LONG.ENDIF, ( -- )

LONG.ENDIF, is used in assembly coded routines to mark the end of a conditional LONG.IF, structure. LONG.ENDIF, and LONG.THEN, are synonyms. Use as:

condition LONG.IF,    . . . .
LONG.ELSE,    . . . .
LONG.ENDIF, 

When executed, LONG.ENDIF, resolves the branch instructions used in the conditional structure. When the code compiled by the control structure is executed, the code between LONG.IF, and LONG.ELSE, is executed if the condition is true, and then control passes to the code following LONG.ENDIF,. If the condition is false, the code between LONG.ELSE, and LONG.ENDIF, is executed, and execution continues with the code following LONG.ENDIF,. An alternate form is

condition LONG.IF, . . . . LONG.ENDIF, 

When the code compiled by this control structure is executed, the code between LONG.IF, and LONG.ENDIF, is executed if the condition is true, and is not executed if the condition is false. This code compiles a long branch instruction, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-end-if-comma"

LONG.IF, ( condition -- )

Used in assembly coded routines to mark the start of a conditional structure. Use as:

condition LONG.IF,    . . . .
LONG.ELSE,    . . . .
LONG.ENDIF,   ( or LONG.THEN,) 

or

condition LONG.IF,    . . . .
LONG.ENDIF,   ( or LONG.THEN,) 

When the branch compiled by LONG.IF, is executed, the code following LONG.IF, is executed if the condition is met, otherwise control is transferred to the code following LONG.ELSE, or LONG.ENDIF,. (LONG.THEN, and LONG.ENDIF, are synonyms). This code construct compiles long branch instructions, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-if-comma"

LONG.REPEAT, ( -- )

LONG.REPEAT, is used to designate the end of an assembly coded structure.

LONG.BEGIN,          . . . .
condition.flag LONG.WHILE,    . . . .
LONG.REPEAT, 

This code construct compiles long branch instructions, allowing the loop to span any number of code bytes on a single page.

See also LONG.BEGIN, and LONG.WHILE,
Pronunciation: "long-repeat-comma"

LONG.THEN, ( -- )

LONG.THEN, is used in assembly coded routines to mark the end of a conditional LONG.IF, structure. It is a synonym for LONG.ENDIF,.

See also LONG.ENDIF,
Pronunciation: "long-then-comma"

LONG.UNTIL, ( condition -- )

Designates the end of an assembly coded looping structure and resolves branch instructions according to the specified condition. Use as:

LONG.BEGIN,       . . . code to be executed . . .
condition LONG.UNTIL, 

If the condition is true, the loop terminates and execution continues with the code following LONG.UNTIL,. If the condition is false, looping continues and execution passes to the code following LONG.BEGIN,. This code construct compiles long branch instructions, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-until-comma"

LONG.WHILE, ( condition -- )

Used in assembly coded routines to mark the beginning of the "while true" portion of a LONG.BEGIN, . . . LONG.WHILE, . . . LONG.REPEAT, loop. Use as:

LONG.BEGIN,       . . . .
condition LONG.WHILE,   . . . .
LONG.REPEAT, 

When executed, LONG.WHILE, causes a branch instruction to be compiled into the dictionary.

When the compiled code is executed:

If the condition is true, the loop continues and the code between LONG.WHILE, and LONG.REPEAT, are executed, after which control is transferred to the code following LONG.BEGIN,. If the condition is false, the loop terminates and execution continues with the code following LONG.REPEAT,. This code construct compiles long branch instructions, allowing the loop to span any number of code bytes on a single page.
Pronunciation: "long-while-comma"

LS ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P ≤ Q using unsigned math. Alternate interpretation: Condition is true if either C or Z in the condition code register is set.
Pronunciation: "lower-or-same"

LSL ( [arg]\mode -- )

Compiles the opcode sequence for the LSL instruction into the dictionary. When later executed, this code causes a logical shift left of the 8-bit operand which is specified by arg and mode. The C (carry) bit in the CCR is loaded from the most significant bit of arg, and 0 is shifted into the least significant bit. The accumulator-offset modes do not require an arg input.
Pronunciation: "logical-shift-left"

LSLA ( -- )

Compiles the opcode sequence for the LSLA instruction into the dictionary. When later executed, this code causes a logical shift left of the contents of accumulator A. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator A, and 0 is shifted into the least significant bit.
Pronunciation: "logical-shift-left-a"

LSLB ( -- )

Compiles the opcode sequence for the LSLB instruction into the dictionary. When later executed, this code causes a logical shift left of the contents of accumulator B. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator B, and 0 is shifted into the least significant bit.
Pronunciation: "logical-shift-left-b"

LSLD ( -- )

Compiles the opcode sequence for the LSLD instruction into the dictionary. When later executed, this code causes a logical shift left of the contents of accumulator D. The C (carry) bit in the CCR is loaded from the most significant bit of accumulator D, and 0 is shifted into the least significant bit.
Pronunciation: "logical-shift-left-d"

LSR ( [arg]\mode -- )

Compiles the opcode sequence for the LSR instruction into the dictionary. When later executed, this code causes a logical shift right of the contents of the operand specified by arg and mode. The C (carry) bit in the CCR is loaded from the least significant bit of arg. 0 is shifted into the most significant bit. The accumulator-offset modes do not require an arg input.
Pronunciation: "logical-shift-right"

LSRA ( -- )

Compiles the opcode sequence for the LSRA instruction into the dictionary. When later executed, this code causes a logical shift right of the contents of accumulator A. The C (carry) bit in the CCR is loaded from the least significant bit of accumulator A. 0 is shifted into the most significant bit.
Pronunciation: "logical-shift-right-a"

LSRB ( -- )

Compiles the opcode sequence for the LSRB instruction into the dictionary. When later executed, this code causes a logical shift right of the contents of accumulator B. The C (carry) bit in the CCR is loaded from the least significant bit of accumulator B. 0 is shifted into the most significant bit.
Pronunciation: "logical-shift-right-b"

LSRD ( -- )

Compiles the opcode sequence for the LSRD instruction into the dictionary. When later executed, this code causes a logical shift right of the contents of accumulator D. The C (carry) bit in the CCR is loaded from the least significant bit of accumulator D. 0 is shifted into the most significant bit.
Pronunciation: "logical-shift-right-d"

LT ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P < Q using signed math. Alternate interpretation: Condition is true if the N bit is set and V bit is clear, or the N bit is clear and the V bit is set in the condition code register.
Pronunciation: "less-than"

MAXA ( [arg]\mode -- )

Compiles the opcode sequence for the MAXA instruction into the dictionary. When later executed, this code performs an 8-bit unsigned “max” operation. The code places into the A register the larger of the unsigned 8 bits referenced by the input arguments, or the unsigned contents of A. The accumulator-offset modes do not require an arg input.
Pronunciation: “-max-a”

MAXM ( [arg]\mode -- )

Compiles the opcode sequence for the MAXM instruction into the dictionary. When later executed, this code performs an 8-bit unsigned “max” operation. The code places into the location referenced by the input arguments the larger of the unsigned 8 bits referenced by the input arguments, or the unsigned contents of A. The accumulator-offset modes do not require an arg input.
Pronunciation: “max-m”

MEM ( -- )

Compiles the opcode sequence for the MEM instruction into the dictionary. When later executed, this code determines the grade of membership for a fuzzy logic implementation. Consult the Motorola HC12 assembly instruction glossary for details.
Pronunciation: “membership”

MI ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q = R, indicates the condition R < 0 using signed math. Alternate interpretation: Condition is true if the N bit in the condition code register is set.
Pronunciation: "minus"

MINA ( [arg]\mode -- )

Compiles the opcode sequence for the MINA instruction into the dictionary. When later executed, this code performs an 8-bit unsigned “min” operation. The code places into the A register the smaller of the unsigned 8 bits referenced by the input arguments, or the unsigned contents of A. The accumulator-offset modes do not require an arg input.
Pronunciation: “min-a”

MINM ( [arg]\mode -- )

Compiles the opcode sequence for the MINM instruction into the dictionary. When later executed, this code performs an 8-bit unsigned “min” operation. The code places into the location referenced by the input arguments the smaller of the unsigned 8 bits referenced by the input arguments, or the unsigned contents of A. The accumulator-offset modes do not require an arg input.
Pronunciation: “min-m”

MOVB ( [src.arg]\src.mode\[dest.arg]\dest.mode -- )

Compiles the opcode sequence for the MOVB instruction into the dictionary. When later executed, this code moves one byte from the source specified by src.arg and src.mode to the destination specified by dest.arg and dest.mode. The accumulator-offset modes do not require an arg input. The following source-destination combinations of addressing modes are allowed:

IMM-EXT   IMM-IDX   EXT-EXT   EXT-IDX   IDX-EXT   IDX-IDX

where IMM is immediate data, EXT is extended addressing, and IDX is indexed addressing. The assembler does not “compensate” for the varying instruction lengths in PC-relatives modes; consult the Motorola HC12 assembly instruction glossary for further details.
Pronunciation: “move-byte”

MOVW ( [src.arg]\src.mode\[dest.arg]\dest.mode -- )

Compiles the opcode sequence for the MOVW instruction into the dictionary. When later executed, this code moves one 16-bit word from the source specified by src.arg and src.mode to the destination specified by dest.arg and dest.mode. The accumulator-offset modes do not require an arg input. The following source-destination combinations of addressing modes are allowed:

IMM-EXT   IMM-IDX   EXT-EXT   EXT-IDX   IDX-EXT   IDX-IDX

where IMM is immediate data, EXT is extended addressing, and IDX is indexed addressing. The assembler does not “compensate” for the varying instruction lengths in PC-relatives modes; consult the Motorola HC12 assembly instruction glossary for further details.
Pronunciation: “move-word”

MUL ( -- )

Compiles the opcode sequence for the MUL instruction into the dictionary. When later executed, this code multiplies the contents of accumulator A by the contents of accumulator B and stores the result in accumulator D.
Pronunciation: "multiply"

NE ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q, indicates the condition P not equal to Q. Alternate interpretation: Condition is true if the Z bit in the condition code register is clear.
Pronunciation: "not-equal"

NEG ( [arg]\mode -- )

Compiles the opcode sequence for the NEG instruction into the dictionary. When later executed, this code replaces the contents of the operand specified by arg and mode with its twos complement which is formed by inverting the state of each bit and adding 1. The accumulator-offset modes do not require an arg input.
Pronunciation: "negate"

NEGA ( -- )

Compiles the opcode sequence for the NEGA instruction into the dictionary. When later executed, this code replaces the contents of accumulator A with its twos complement which is formed by inverting the state of each bit and adding 1.
Pronunciation: "negate-a"

NEGB ( -- )

Compiles the opcode sequence for the NEGB instruction into the dictionary. When later executed, this code replaces the contents of accumulator B with its twos complement which is formed by inverting the state of each bit and adding 1.
Pronunciation: "negate-b"

NEVER ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Indicates a "never true" condition.

NOP ( -- )

Compiles the opcode sequence for the NOP instruction into the dictionary. When later executed, this code does nothing.
Pronunciation: "no-op"

ORAA ( [arg]\mode -- )

Compiles the opcode sequence for the ORAA instruction into the dictionary. When later executed, this code performs a logical OR operation between the contents of accumulator A and the contents of the operand specified by arg and mode. The result is stored in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "or-accumulator-a"

ORAB ( [arg]\mode -- )

Compiles the opcode sequence for the ORAB instruction into the dictionary. When later executed, this code performs a logical OR operation between the contents of accumulator B and the contents of the operand specified by arg and mode. The result is stored in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "or-accumulator-b"

ORCC ( arg\mode -- | mode must be IMM )

Compiles the opcode sequence for the ORCC instruction into the dictionary. When later executed, this code performs the logical OR of the operand (specified by immediate data arg and mode IMM) and the contents of the condition code register, and places the result in the condition code register.
Pronunciation: "or-c-c"

PL ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. Used after a comparison of the form P - Q = R, indicates the condition R ≥ 0 using signed math. Alternate interpretation: Condition is true if the N bit in the condition code register is clear.
Pronunciation: "plus"

PSHA ( -- )

Compiles the opcode sequence for the PSHA instruction into the dictionary. When later executed, this code stores the contents of accumulator A at the next available location on the return stack pointed to by the S register and decrements the S register.
Pronunciation: "push-a"

PSHB ( -- )

Compiles the opcode sequence for the PSHB instruction into the dictionary. When later executed, this code stores the contents of accumulator B at the next available location on the return stack pointed to by the S register and decrements the S register.
Pronunciation: "push-b"

PSHC ( -- )

Compiles the opcode sequence for the PSHC instruction into the dictionary. When later executed, this code stores the contents of the condition code register at the next available location on the return stack pointed to by the S register and decrements the S register.
Pronunciation: "push-c"

PSHD ( -- )

Compiles the opcode sequence for the PSHD instruction into the dictionary. When later executed, this code stores the contents of accumulator D at the next available locations on the return stack pointed to by the S register and decrements the S register by 2.
Pronunciation: "push-d"

PSHX ( -- )

Compiles the opcode sequence for the PSHX instruction into the dictionary. When later executed, this code stores the contents of index register X at the next available locations on the return stack pointed to by the S register and decrements the S register by 2.
Pronunciation: "push-x"

PSHY ( -- )

Compiles the opcode sequence for the PSHY instruction into the dictionary. When later executed, this code stores the contents of index register Y at the next available locations on the return stack pointed to by the S register and decrements the S register by 2.
Pronunciation: "push-y"

PULA ( -- )

Compiles the opcode sequence for the PULA instruction into the dictionary. When later executed, this code pops the top value off the return stack (pointed to by the S register) into accumulator A and increments the S register.
Pronunciation: "pull-a"

PULB ( -- )

Compiles the opcode sequence for the PULB instruction into the dictionary. When later executed, this code pops the top value off the return stack (pointed to by the S register) into accumulator B and increments the S register.
Pronunciation: "pull-b"

PULC ( -- )

Compiles the opcode sequence for the PULC instruction into the dictionary. When later executed, this code pops the top value off the return stack (pointed to by the S register) into the condition code register and increments the S register.
Pronunciation: "pull-c"

PULD ( -- )

Compiles the opcode sequence for the PULD instruction into the dictionary. When later executed, this code pops the top 2 bytes off the return stack (pointed to by the S register) into accumulator D and increments the S register by 2.
Pronunciation: "pull-d"

PULX ( -- )

Compiles the opcode sequence for the PULX instruction into the dictionary. When later executed, this code pops the top 2 bytes off the return stack (pointed to by the S register) into index register X and increments the S register by 2.
Pronunciation: "pull-x"

PULY ( -- )

Compiles the opcode sequence for the PULY instruction into the dictionary. When later executed, this code pops the top 2 bytes off the return stack (pointed to by the S register) into index register Y and increments the S register by 2.
Pronunciation: "pull-y"

REL ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the relative addressing mode should be used by an instruction opcode. The REL mode never has to be explicitly specified in an assembly instruction, so this is a do-nothing instruction that is present to preserve backward-compatibility with prior versions of the assembler.
Pronunciation: "relative"

REPEAT, ( -- )

REPEAT, is used to designate the end of an assembly coded structure as,

BEGIN,          . . . .
condition.flag WHILE,    . . . .
REPEAT, 

The backwards branch compiled by this instruction is limited to –128 bytes; if a longer branch is needed, use the LONG.BEGIN, …LONG.WHILE,…LONG.REPEAT, construction.

See also BEGIN, and WHILE,
Pronunciation: "repeat-comma"

REV ( -- )

Compiles the opcode sequence for the REV instruction into the dictionary. When later executed, this code performs an unweighted evaluation of a list of rules, using fuzzy input values to produce fuzzy outputs. Consult the Motorola HC12 assembly instruction glossary for details.
Pronunciation: “rule-evaluation”

REVW ( -- )

Compiles the opcode sequence for the REVW instruction into the dictionary. When later executed, this code performs a weighted evaluation of a list of rules, using fuzzy input values to produce fuzzy outputs. Consult the Motorola HC12 assembly instruction glossary for details.
Pronunciation: “rule-evaluation-weighted”

ROL ( [arg]\mode -- )

Compiles the opcode sequence for the ROL instruction into the dictionary. When later executed, this code shifts the bits in the operand specified by arg and mode left by one bit. The C (carry) bit is shifted into the least significant bit of arg, and the most significant bit in arg is shifted into C. The accumulator-offset modes do not require an arg input.
Pronunciation: "rotate-left"

ROLA ( -- )

Compiles the opcode sequence for the ROLA instruction into the dictionary. When later executed, this code shifts the bits in accumulator A left by one bit. The C (carry) bit is shifted into the least significant bit of accumulator A, and the most significant bit in accumulator A is shifted into C.
Pronunciation: "rotate-left-a"

ROLB ( -- )

Compiles the opcode sequence for the ROLB instruction into the dictionary. When later executed, this code shifts the bits in accumulator B left by one bit. The C (carry) bit is shifted into the least significant bit of accumulator B, and the most significant bit in accumulator B is shifted into C.
Pronunciation: "rotate-left-b"

ROR ( [arg]\mode -- )

Compiles the opcode sequence for the ROR instruction into the dictionary. When later executed, this code shifts the bits in the operand specified by arg and mode right by one bit. The C (carry) bit is shifted into the most significant bit of arg, and the least significant bit in arg is shifted into C. The accumulator-offset modes do not require an arg input.
Pronunciation: "rotate-right"

RORA ( -- )

Compiles the opcode sequence for the RORA instruction into the dictionary. When later executed, this code shifts the bits in accumulator A right by one bit. The C (carry) bit is shifted into the most significant bit of accumulator A, and the least significant bit in accumulator A is shifted into C.
Pronunciation: "rotate-right-a"

RORB ( -- )

Compiles the opcode sequence for the RORB instruction into the dictionary. When later executed, this code shifts the bits in accumulator B right by one bit. The C (carry) bit is shifted into the most significant bit of accumulator B, and the least significant bit in accumulator B is shifted into C.
Pronunciation: "rotate-right-b"

RTC ( -- )

Compiles the opcode sequence for the RTC instruction into the dictionary. When later executed, this code restores the page (PPAGE register contents) with a byte pulled from the stack, and restores the program counter PC with a 16-bit value pulled from the stack, thereby resuming execution just after the point where the subroutine was called. Use this instruction to terminate subroutines invoked with CALL,.

See also RTS
Pronunciation: "return-from-call"

RTI ( -- )

Compiles the opcode sequence for the RTI instruction into the dictionary. When later executed, this code restores accumulators A and B, the condition code register CC, and registers X, Y and PC with values pulled from the stack.
Pronunciation: "return-from-interrupt"

RTS ( -- )

Compiles the opcode sequence for the RTS instruction into the dictionary. When later executed, this code restores the program counter with a value pulled from the stack, thereby resuming execution just after the point where the subroutine was called. Use this instruction to terminate subroutines invoked with JSR.

See also RTC
Pronunciation: "return-from-subroutine"

S, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that the stack pointer register S is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "s-register"

SBA ( -- )

Compiles the opcode sequence for the SBA instruction into the dictionary. When later executed, this code subtracts the contents of accumulator B from accumulator A and stores the result in accumulator A. The contents of accumulator B are not affected.
Pronunciation: "subtract-b-from-a"

SBCA ( [arg]\mode -- )

Compiles the opcode sequence for the SBCA instruction into the dictionary. When later executed, this code subtracts the contents of the operand specified by arg and mode and the contents of C from accumulator A and stores the result in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "subtract-with-carry-a"

SBCB ( [arg]\mode -- )

Compiles the opcode sequence for the SBCB instruction into the dictionary. When later executed, this code subtracts the contents of the operand specified by arg and mode and the contents of C from accumulator B and stores the result in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "subtract-with-carry-b"

SEC ( -- )

Compiles the opcode sequence for the SEC instruction into the dictionary. When later executed, this code sets the C (carry) bit in the condition code register.
Pronunciation: "set-carry"

SEI ( -- )

Compiles the opcode sequence for the SEI instruction into the dictionary. When later executed, this code sets the I (global interrupt enable) bit in the condition code register. When the I bit is set, all maskable interrupts are disabled.
Pronunciation: "set-interrupt-mask"

SEV ( -- )

Compiles the opcode sequence for the SEV instruction into the dictionary. When later executed, this code sets the V (2's complement overflow) bit in the condition code register.
Pronunciation: "set-overflow-bit"

SEX ( reg.arg1\reg.arg2 -- | reg.arg1 = source register, reg.arg2 = destination register )

Compiles the opcode sequence for the SEX instruction into the dictionary. When later executed, this code sign extends the contents of the source register into the destination register. The source reg.arg1 parameter can be any of the following:

A,   B,  CCR,  

and the destination reg.arg2 parameter can be any of the following:

D,   X,   Y,    S,

This is a subset of the TFR instruction, with error checking.
Pronunciation: “sign-extend”

STAA ( [arg]\mode -- )

Compiles the opcode sequence for the STAA instruction into the dictionary. When later executed, this code stores the contents of accumulator A into the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "store-accumulator-a"

STAB ( [arg]\mode -- )

Compiles the opcode sequence for the STAB instruction into the dictionary. When later executed, this code stores the contents of accumulator B into the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "store-accumulator-b"

STD ( [arg]\mode -- )

Compiles the opcode sequence for the STD instruction into the dictionary. When later executed, this code stores the contents of accumulator D into the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.
Pronunciation: "store-d"

STOP ( -- )

Compiles the opcode sequence for the STOP instruction into the dictionary. When later executed, this code halts all system clocks and places the system in a minimum power consumption mode if the S bit in the CCR register is clear. If the S bit is set, STOP is disabled and acts like a NOP. Recovery is accomplished by a reset, or an active low signal on XIRQ, or a non-masked IRQ interrupt.

STS ( [arg]\mode -- )

Compiles the opcode sequence for the STS instruction into the dictionary. When later executed, this code stores the contents of the S register (which is the return stack pointer) at the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.

NOTE: If this instruction mode auto-increments or auto-decrements the S register, the value stored into S is the value of S before the instruction executed.
Pronunciation: "store-s"

STX ( [arg]\mode -- )

Compiles the opcode sequence for the STX instruction into the dictionary. When later executed, this code stores the contents of index register X at the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.

NOTE: If this instruction mode auto-increments or auto-decrements the X register, the value stored into X is the value of X before the instruction executed.
Pronunciation: "store-x"

STY ( [arg]\mode -- )

Compiles the opcode sequence for the STY instruction into the dictionary. When later executed, this code stores the contents of index register Y at the effective address specified by arg and mode. The accumulator-offset modes do not require an arg input.

NOTE: If this instruction mode auto-increments or auto-decrements the Y register, the value stored into Y is the value of Y before the instruction executed.
Pronunciation: "store-y"

SUBA ( [arg]\mode -- )

Compiles the opcode sequence for the SUBA instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator A and places the result in accumulator A. The accumulator-offset modes do not require an arg input.
Pronunciation: "subtract-a"

SUBB ( [arg]\mode -- )

Compiles the opcode sequence for the SUBB instruction into the dictionary. When later executed, this code subtracts the operand specified by arg and mode from the contents of accumulator B and places the result in accumulator B. The accumulator-offset modes do not require an arg input.
Pronunciation: "subtract-b"

SUBD ( [arg]\mode -- )

Compiles the opcode sequence for the SUBD instruction into the dictionary. When later executed, this code subtracts the contents of the operand specified by arg and mode from the contents of accumulator D and places the result in accumulator D. The accumulator-offset modes do not require an arg input.
Pronunciation: "subtract-d"

SWI ( -- )

Compiles the opcode sequence for the SWI instruction into the dictionary. When later executed, this code invokes a software interrupt. It stores the CCR, accumulators A and B, and registers X, Y and PC on the stack. The stack pointer is decremented by 1 for each byte stored on the stack. The I bit in the CCR register is set. The PC register is then loaded with the address located at the interrupt vector for SWI, and instruction execution resumes at this location.
Pronunciation: "software interrupt"

TAB ( -- )

Compiles the opcode sequence for the TAB instruction into the dictionary. When later executed, this code transfers the contents of accumulator A to accumulator B.
Pronunciation: "transfer-a-to-b"

TAP ( -- )

Compiles the opcode sequence for the TAP instruction into the dictionary. When later executed, this code transfers the contents of accumulator A to the condition code register.
Pronunciation: "transfer-a-to-condition-code-register"

TBA ( -- )

Compiles the opcode sequence for the TBA instruction into the dictionary. When later executed, this code transfers the contents of accumulator B to accumulator A.
Pronunciation: "transfer-b-to-a"

TBEQ ( arg\reg.arg -- )

Compiles the opcode sequence for the TBEQ instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code tests the specified register and, if Z in CCR is set, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "test-and-branch-if-equal"

TBL ( [arg]\mode -- )

Compiles the opcode sequence for the TBL instruction into the dictionary. When later executed, this code performs a table lookup and interpolate operation. The input parameters specify an index register that in turn points into a table of (x,y) pairs. Any indexed addressing mode, except indirect modes or 9- and 16-bit offset modes can be used. The B register must be pre-loaded with a binary fraction (radix point to the left of the most significant bit in B), and this routine interpolates between the pointed to (x,y) pair and the succeeding (x,y) pair in the table based on the specified fraction. The interpolated Y value is returned in A. The accumulator-offset modes do not require an arg input.
Pronunciation: “table-lookup”

TBNE ( arg\reg.arg -- )

Compiles the opcode sequence for the TBNE instruction into the dictionary; the arg is a 9-bit signed relative offset (-256 ≤ arg ≤ 255), and reg.arg is one of the following:

A,   B,   D,   X,   Y,    S,

When later executed, this code tests the specified register and, if Z in CCR is clear, executes a branch to the address equal to PC + arg + 3.
Pronunciation: "test-and-branch-if-not-equal"

TFR ( reg.arg1\reg.arg2 -- | reg.arg1 = source register, reg.arg2 = destination register )

Compiles the opcode sequence for the TFR instruction into the dictionary. When later executed, this code transfers the contents of the source register into the destination register. The source and destination reg.arg parameters can be any of the following:

A,   B,  CCR,  D,   X,   Y,    S,

Pronunciation: “transfer-register”

THEN, ( -- )

THEN, is used in assembly coded routines to mark the end of a conditional IF, structure. It is a synonym for ENDIF,.

See also ENDIF,
Pronunciation: "then-comma"

TPA ( -- )

Compiles the opcode sequence for the TPA instruction into the dictionary. When later executed, this code transfers the contents of the condition code register into accumulator A.
Pronunciation: "transfer-condition-code-register-to-a"

TST ( [arg]\mode -- )

Compiles the opcode sequence for the TST instruction into the dictionary. When later executed, this code subtracts zero from the contents of the operand specified by arg and mode and sets the condition code register's bits accordingly. The operand is unaffected by the subtraction. The accumulator-offset modes do not require an arg input.
Pronunciation: "test"

TSTA ( -- )

Compiles the opcode sequence for the TSTA instruction into the dictionary. When later executed, this code subtracts zero from the contents of accumulator A and sets the condition code register's bits accordingly. Accumulator A is unaffected.
Pronunciation: "test-a"

TSTB ( -- )

Compiles the opcode sequence for the TSTB instruction into the dictionary. When later executed, this code subtracts zero from the contents of accumulator B and sets the condition code register's bits accordingly. Accumulator B is unaffected.
Pronunciation: "test-b"

TSX ( -- )

Compiles the opcode sequence for the TSX instruction into the dictionary. When later executed, this code loads index register X with the contents of the S register (which is the return stack pointer). After this operation the X register points to the top item on the return stack.
Pronunciation: "transfer-stack-to-x"

TSY ( -- )

Compiles the opcode sequence for the TSY instruction into the dictionary. When later executed, this code loads index register Y with the contents of the S register (which is the return stack pointer). After this operation the Y register points to the top item on the return stack.
Pronunciation: "transfer-s-to-y"

TXS ( -- )

Compiles the opcode sequence for the TXS instruction into the dictionary. When later executed, this code loads the S register (which is the return stack pointer) with the contents of the index register X.
Pronunciation: "transfer-x-to-s"

TYS ( -- )

Compiles the opcode sequence for the TYS instruction into the dictionary. When later executed, this code loads the S register (which is the return stack pointer) with the contents of the index register Y.
Pronunciation: "transfer-y-to-s"

UNTIL, ( condition -- )

UNTIL, designates the end of an assembly coded looping structure and resolves branch instructions according to the specified condition. Use as:

BEGIN,       . . . code to be executed . . .
condition UNTIL, 

If the condition is true, the loop terminates and execution continues with the code following UNTIL,. If the condition is false, looping continues and execution passes to the code following BEGIN,. The backwards branch compiled by this code is limited to -128 bytes; if a longer branch is needed, use the LONG.BEGIN, …LONG.UNTIL, construction.
Pronunciation: "until-comma"

VC ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. The condition is true when the V (2's complement overflow) flag in the condition code register is 0.
Pronunciation: "overflow-clear"

VS ( -- condition )

Used within a code definition, leaves a condition flag on the data stack. The condition is true when the V (2's complement overflow) flag in the condition code register is 1.
Pronunciation: "overflow-set"

WAI ( -- )

Compiles the opcode sequence for the WAI instruction into the dictionary. When later executed, this code saves the condition code register, accumulators A and B, and register X, Y and PC on the stack. The stack pointer is decremented for each byte stored. The CPU the enters a lower power consumption mode, while waiting for an interrupt which has not been masked. When an interrupt is recognized, the CPU sets the I bit in the CCR, and execution resumes at the address stored in the appropriate interrupt vector.
Pronunciation: "wait-for-interrupt"

WAV ( -- )

Compiles the opcode sequence for the WAV instruction into the dictionary. When later executed, this code performs a weighted average calculation based on values stored in memory to support fuzzy logic rule evaluation. Consult the Motorola HC12 assembly instruction glossary for details.
Pronunciation: “weighted-average”

WHILE, ( condition -- )

WHILE, is used in assembly coded routines to mark the beginning of the "while true" portion of a BEGIN, . . . WHILE, . . . REPEAT, loop. Use as:

BEGIN,       . . . .
condition WHILE,   . . . .
REPEAT, 

When executed, WHILE, causes a branch instruction to be compiled into the dictionary.

When the compiled code is executed:

If the condition is true, the loop continues and the code between WHILE, and REPEAT, are executed, after which control is transferred to the code following BEGIN,. If the condition is false, the loop terminates and execution continues with the code following REPEAT,. The branches compiled by this code construct are limited to the range –128 to +127 bytes; if a longer loop is needed, use the LONG.BEGIN, …LONG.WHILE,… LONG.REPEAT, construction.
Pronunciation: "while-comma"

X, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that the index register X is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "x-register"

XCODE ( <name> -- )

Starts a C-callable assembly coded definition. Consult the main glossary.
Pronunciation: "x-code"

XGDX ( -- )

Compiles the opcode sequence for the XGDX instruction into the dictionary. When later executed, this code exchanges the contents of accumulator D with the contents of index register X.
Pronunciation: "exchange-d-and-x"

XGDY ( -- )

Compiles the opcode sequence for the XGDY instruction into the dictionary. When later executed, this code exchanges the contents of accumulator D with the contents of index register Y.
Pronunciation: "exchange-d-and-y"

Y, ( -- reg.arg )

Used within a code definition, leaves a constant on the stack indicating that the index register Y is to be used by an opcode. This register specifier can be used with the DBEQ, DBNE, IBEQ, IBNE, TBEQ, TBNE, EXG, TFR, and SEX opcodes, and the +LOOP, and –LOOP, directives.
Pronunciation: "y-register"

[D,PC] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D indirect indexed addressing mode relative to the PC (program counter) register should be used by an instruction opcode. This mode adds the value in D to the contents of PC to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-d-comma-p-c"

[D,S] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D indirect indexed addressing mode relative to the S (stack pointer) register should be used by an instruction opcode. This mode adds the value in D to the contents of S to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-d-comma-s"

[D,X] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D indirect indexed addressing mode relative to the index register X register should be used by an instruction opcode. This mode adds the value in D to the contents of X to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-d-comma-x"

[D,Y] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the accumulator D indirect indexed addressing mode relative to the index register Y register should be used by an instruction opcode. This mode adds the value in D to the contents of Y to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-d-comma-y"

[IND16,PC] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant indirect indexed addressing mode relative to the PC (program counter) register should be used by an instruction opcode. This mode adds the constant value to the contents of PC to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-sixteen-comma-p-c"

[IND16,S] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant indirect indexed addressing mode relative to the S (stack pointer) register should be used by an instruction opcode. This mode adds the constant value to the contents of S to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-sixteen-comma-s"

[IND16,X] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant indirect indexed addressing mode relative to the index register X register should be used by an instruction opcode. This mode adds the constant value to the contents of X to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-sixteen-comma-x"

[IND16,Y] ( -- mode )

Used within a code definition, leaves a constant on the stack indicating that the 16-bit constant indirect indexed addressing mode relative to the index register Y register should be used by an instruction opcode. This mode adds the constant value to the contents of Y to form the address of a memory location that contains a pointer to the value to be acted upon by the instruction.
Pronunciation: "indirect-indexed-sixteen-comma-y"