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Appendix H - How To Use Additional Features of the 8 Bit A/D

The built-in driver routines for the 8 bit A/D are described in Chapter 6 of this manual. They are easy to use and address the needs of most applications. If the built-in routines meet your requirements, you need not read this appendix. If, on the other hand, you wish to gain a more detailed understanding of the operation of the 8 bit A/D, or need to use one of its special operating modes, the information in this appendix may prove useful.

The A/D drivers built into QED-Forth sample a single specified channel one or more times as described in Chapter 6 of this manual. Sampling frequencies for acquiring and storing data in memory reach 40 kHz with an 8 MHz crystal, which is close to the optimal attainable rate. Some applications, however, may require the use of conversion features that are not supported by the device driver routines. These include the ability of the 8 bit A/D converter to continuously sample four different analog inputs in rapid succession. This appendix describes the inner workings of the 68HC11's A/D converter and presents code that simplifies the use of all the available operating modes.

The 8 bit A/D in the 68HC11 performs four conversions at a time and stores the four sample results in A/D result registers ADR1, ADR2, ADR3 and ADR4 (HC11 p.12-15, F1 11-5). The converter can be configured to take four samples of a single analog input channel, or to take one sample from each of four channels grouped as channels 0 through 3 or channels 4 through 7 (HC11 pp.12-13...12-15, F1 p.11-3).

With each conversion request to the A/D, you can sample a single channel four times, or four channels one time each. When a single channel is sampled four times, the four consecutive results are stored in registers ADR1, ADR2, ADR3 and ADR4, respectively. When four channels are sampled one time each, the results are stored in the registers according to the following table:

Group1 Group2 Result Location

Whether you request samples from a single channel, or a group of channels, the sampling can be performed discretely or continuously. When sampling is done discretely, a single measurement is stored in each A/D result register and then the conversion process stops. Continuous sampling constantly updates each A/D result register with the most recent measurement, and the result registers may be read at any time after an initial delay.


Initiating the Conversion

The conversion process is initiated by storing a "sample request value" to the A/D control register named ADCTL (HC11 pp.12-13...12-15). The sample request value indicates the channel(s) to be converted and the method to be used, either discrete or continuous. The sample request value is determined by a bit named SCAN, one named MULT (multiple), and a group of channel bits named CD, CC, CB and CA (HC11 pp.12-13...12-15, F1 p.11-4). SCAN determines whether the sampling method will be discrete or continuous. MULT determines whether conversions will be made for a group of channels or an individual channel. CD, CC, CB and CA form a 4-bit code that identifies the channel or group of channels to be sampled.

The conversion process begins as soon as a sample request value is stored in the ADCTL control register. The conversion result registers may be read after a conversion complete flag, CCF, in the ADCTL register is set (F1 p.11-4). The CCF flag is usually polled, as there is no interrupt mask supporting this bit. Each sample conversion takes 32 cycles, corresponding to 16 microseconds with an 8 MHz crystal, or 8 microseconds with a 16 MHz crystal. The CCF is automatically cleared by a write to the ADCTL control register. If you are sure that the A/D conversion will be complete by the time you read the results, you can ignore the state of the CCF flag.

In sum, A/D conversions are performed by simply determining the appropriate sample request value needed for the desired conversion, storing that value into the ADCTL register, polling the CCF bit until it is set, and then reading the appropriate A/D result registers.


A/D Utility Words

The following code demonstrates the use of all of the operating modes of the 8 bit A/D. Note that most applications can simply use the driver routines that are built into QED-Forth as described in Chapter 6 of this manual.

\ A/D subsystem register addresses
8030 REGISTER: ADCTL    \ for a conversion, store a proper value here
8031 REGISTER: ADR1    \ a/d result register 1
8032 REGISTER: ADR2    \ a/d result register 2
8033 REGISTER: ADR3    \ a/d result register 3
8034 REGISTER: ADR4    \ a/d result register 4
\ Channel/Group Identifiers:
10    CONSTANT    AN0-3    \ identifies channels 0..3
14    CONSTANT    AN4-7    \ identifies channels 4..7
\ Analog channels AN0 through AN7 are represented by numbers 0...7
00    CONSTANT    DISCRETE.SAMPLING    \ discrete sampling mask
20    CONSTANT    CONTINUOUS.SAMPLING    \ continuous sampling mask
80    CONSTANT    CONVERSION.COMPLETE    \ bit mask for flag in ADCTL register
CODE POLL ( mask\addr --  )    \ addr must be in common memory!
    \ waits until the bits set in the mask are also set in the byte stored at addr.
    \ this routine is assembly coded for speed
    BEGIN,            \ begin wait loop
        0 IND,Y LDX        \ X <- addr
        0 IND,X LDAB    \ B <- byte contents of addr
        3 IND,Y ANDB    \ AND contents of addr with the mask
        3 IND,Y CMPB    \ loop until the result equals the mask
    4 IMM LDAB
    ABY                ( -- ) \ drop 2 items to clear stack
\ START.CONVERSION, given a channel/group id and a continuous or discrete
\ mode mask, combines the masks using a logical OR operation and stores
\ the resulting  sample request value in ADCTL to initiate a conversion.
: START.CONVERSION    (\continuous.or.discrete -- )
\ PRINT.A/D.RESULTS polls the ADCTL register, waiting until the conversion
\ is complete.  It then prints the values found in the A/D result registers.
  : PRINT.A/D.RESULTS ( -- )
    CONVERSION.COMPLETE ADCTL DROP POLL    \ wait til conversion is done
    CR ." Result#1 = " ADR1 C@ .        \ print the 4 results
    CR ." Result#2 = " ADR2 C@ .
    CR ." Result#3 = " ADR3 C@ .
    CR ." Result#4 = " ADR4 C@ .

After turning on the A/D by calling A/D.ON, we can start a conversion. Just place on the stack the appropriate channel number or the name of the group identifier defined above, followed by either DISCRETE.SAMPLING (if you want only 1 set of 4 conversions) or CONTINUOUS.SAMPLING (if you want the four result registers to be continuously updated), followed by START.CONVERSION. For example, continuous sampling of analog channel 4 (pin 6 on the Analog I/O bus in Appendix A) is initiated by executing


Continuous sampling of group AN0 through AN3 is initiated by executing


The results can be printed by executing

This page is about: Using 68HC11 MC68HC11F1 A/D Analog to Digital Converter – The built in driver routines for 8 bit A/D are described in Chapter 6 of this manual. They are easy to use and address needs of most applications. If built in routines meet your requirements, you need not read this appendix. If, on other hand, you wish …