The C Programmer’s Guide to the QVGA Controller

The QVGA Controller comprises a stack of three boards: a display backplane, the QVGA Board, and the smaller QED-4-QVGA Board (aka QED-Flash Board). Pin-outs for all I/O connectors on the QED-Flash Board or the QVGA Board are provided here.

Warning – Do Not Connect to System Control Signals

When connecting to the Digital I/O Connector (H2 on the QVGA Board) with a ribbon cable, notch out cable wires 11 through 24. Even short pieces of wire connected to some of these lines may cause intermittent operation of the touchscreen or processor.

When connecting to the Supplemental I/O Connector (H3 on the QED Board) with a ribbon cable, only connect the wires you need, and do not connect to the data bus lines or system control lines.

QED Flash Board Connectors

The pinouts of all of the connectors on the QED–Flash Board are presented below. To locate the connectors on the board, consult Figure B–1 and the white silk–screened labels on the visible side of the QED–Flash Board. The arrows in the figure point to the locations of pin 1 on each connector.

Figure B–1 QED–Flash Board Connectors and Switches. Arrows locate pin 1 of each connector.

Table B‑1 H3: Supplemental I/O Connector

Signal		Pins			Signal
PPB4	–	1	2	–	GND
PPB3	–	3	4	–	+5V
PPC3	–	5	6	–	Vcontrast
PPC0	–	7	8	–	A1
PPB2	–	9	10	–	R//W
PPC1	–	11	12	–	Display.E
PPC2	–	13	14	–	D0
PPB1	–	15	16	–	D1
PPB0	–	17	18	–	D2
DGND	–	19	20	–	D3
HC0*	–	21	22	–	D4
HC1 (PB5)*	–	23	24	–	D5
HC2 (PB6)*	–	25	26	–	D6
HC3 (PB7)*	–	27	28	–	D7
DGND	–	29	30	–	DGND
SNUB	–	31	32	–	+5VDD
V+RAW	–	33	34	–	VEE
* HC0 is generated by the PAL, HC1–HC3 are generated from PB5–PB7 respectively. You should not connect to the shaded signals. Even a short wire connected to these lines may cause malfunction.

Table B‑2 H6: Address/Data Table B‑3 H2: Analog I/O Connector

Signal

Pins

Signal

Pins

Signal

PG7

–

PG6

Vrl

–

Vrh

PG5

–

PG4

PE7/AN7

–

PE6/AN6

PG3

–

PG2

PE5/AN5

–

PE4/AN4

PG1

–

PG0

PE3/AN3

–

PE2/AN2

A15

–

A14

PE1/AN1

–

PE0/AN0

A13

–

A12

12AN7

–

12AN6

A11

–

A10

12AN5

–

12AN4

–

12AN3

–

12AN2

–

12AN1

–

12AN0

–

AGND

–

+5VAN

–

Vin1

–

Vout1

–

Vin2

–

Vout2

–

Vin3

–

Vout3

–

Vin4

–

Vout4

–

Vin5

–

Vout5

–

Vin6

–

Vout6

/RESET

–

R//W

Vin7

–

Vout7

/OE

–

/WE

Vin8

–

Vout8

–

V+Raw

1.5Vref

–

+5V

DGND

–

+5V

Analog Bus V–

–

V+Raw

You should not generally need to connect to the processor's address and data bus. Please consult Mosaic Industries before attempting to connect to these signals.

Processor Port E may be used as either 8–bit A/D inputs (AN0–7) or as digital inputs. 12AN0-7 are 12-bit A/D inputs. Vin1-8 and Vout1-8 are the 8-bit multiplying DAC inputs and outputs.

QVGA Board Connectors

The pin-outs of all of the connectors on the QVGA Board are presented below. To locate the connectors on the board, consult Figure B‑2 and the white silk–screened labels on the visible side of the QVGA Board.

Figure B‑2 Connectors and Switches on the QVGA Controller

Table B‑4 H22: Power Header

Signal		Pins			Signal
GND	–	1	2	–	GND
V+Raw	–	3	4	–	V+Bias
+12 V / +5 V ALT	–	5	6	–	+5 V
+5 VAN	–	7	8	–	+3.3 V
MONO_VEE	–	9	10	–	GND

Table B‑5 Serial 1 Connector Table B‑6 Serial 2 Connector

Signal	Pins				Signal	Signal	Pins				Signal
NC	–	1				NC	–	1
			6	–	DSR1/DTR1				6	–	DSR2/DTR2
TXD1	–	2				TXD2	–	2
			7	–	CTS1				7	–	CTS2/RTS2
RXD1	–	3				RXD2	–	3
			8	–	RTS1				8	–	RTS2/CTS2
DSR1/DTR1	–	4				DSR2/DTR2	–	4
			9	–	NC				9	–	NC
DGND	–	5				DGND	–	5
Notes:						Notes:
NC indicates no connection						NC indicates no connection
Pins 4 and 6 (DSR1/DTR1) are connected.						Pins 4 and 6 (DSR1/DTR1) are connected.
Pins 7 and 8 (CTS1/RTS1) may optionally be connected on the board with zero ohm shorts.						Pins 7 and 8 (CTS1/RTS1) are connected.

Table B‑7 H14: Serial Communications Connector

Signal		Pins			Signal
TxD1	–	1	2	–	RxD1
DGND	–	3	4	–	DGND
XCVR-	–	5	6	–	XCVR+
TxD2	–	7	8	–	RxD2
DGND	–	9	10	–	DGND

Table B‑8 Wildcard Port Header

Signal		Pins			Signal
GND	–	1	2	–	+5V
/IRQ	–	3	4	–	V+Raw
PG1/XMIT-	–	5	6	–	PG0/XMIT+
MOSI/XCV-	–	7	8	–	MISO/XCV+
/RESET	–	9	10	–	SCK
/MOD.CS	–	11	12	–	16 MHz
E	–	13	14	–	R/W
/OE	–	15	16	–	/WE
AD7	–	17	18	–	AD6
AD5	–	19	20	–	AD4
AD3	–	21	22	–	AD2
AD1	–	23	24	–	AD0

Table B‑9 H2, H4: Digital I/O Connector

Signal		Pins			Signal
GND	–	1	2	–	+5V
PA7	–	3	4	–	PA6
PA5	–	5	6	–	PA4
PA3	–	7	8	–	PA2
PA1	–	9	10	–	PA0
PD5//SS	–	11	12	–	PD4/SCK
PD3/MOSI	–	13	14	–	PD2/MISO
E	–	15	16	–	R//W
/OE	–	17	18	–	/WE
/XIRQ	–	19	20	–	/IRQ
PFI Input	–	21	22	–	4xOut
/Reset	–	23	24	–	/Shutdown
PPC7	–	25	26	–	PPC6
PPC5	–	27	28	–	PPC4/RS485.XMIT
PPA7	–	29	30	–	PPA6
PPA5	–	31	32	–	PPA4
PPA3	–	33	34	–	PPA2
PPA1	–	35	36	–	PPA0
AGND	–	37	38	–	+5VAN
DGND	–	39	40	–	V+Raw
Notes:
Headers H2 and H4 are connected in parallel. H4 connects to the QED Board, and H2 is available for you to connect to.
You should not need to connect to the shaded signals. When connecting a ribbon cable to H2 you should notch out the wires corresponding to the shaded signals, pins 11 through 24. Even short lengths of wire connected to these signals may cause intermittent operation of the processor or the touchscreen.

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The C Programmer’s Guide to the QVGA Controller

Table of Contents

Appendix B: Connector Pinouts

QED Flash Board Connectors

QVGA Board Connectors