Digital I/O

The PDQ Single Board Computer (SBC) provides 8 I/O lines controlled by the Enhanced Capture/Timer (ECT), 8 Pulse-Width Modulated (PWM) lines, 8 general purpose digital I/O lines, 16 analog input lines (which may be used as digital inputs), and several communications channels – all derived from its 9S12 microcontroller unit. All of the timer-controlled and PWM signals can be configured as general purpose digital I/O, and the two lines associated with the IIC (Inter-IC) serial bus can also be reconfigured as digital I/O. A maximum of 42 digital inputs and outputs are available on the PDQ Board.

The following table summarizes the available digital I/O lines:

After a power-up or hardware reset, all of the digital I/O lines are configured as inputs, and AN0-15 are configured as analog inputs. All PWM and ECT features are disabled by default after a hardware reset. With the exception of pins AN0-15, the signals listed in the table may be reconfigured as outputs via software commands. Pins AN0-15 are software configurable as either analog or digital inputs as described below.

The maximum number of digital inputs and outputs is 42. Up to 42 can be configured as inputs, and up to 26 as outputs if none are used for the ATD (Analog To Digital) converter or the IIC 2-wire serial bus.

Digital inputs and outputs are very useful in data acquisition, monitoring, and instrument control applications. A low voltage (near 0 Volts) is established on a digital output pin when the processor writes a logical 0 to the corresponding bit in a data register associated with the digital output port. A high voltage (near 5 Volts) is established on the digital output pin when the processor writes a 1 to a corresponding bit in the port’s data register. This allows software to control external events and processes. For example, a C-language application program can use digital outputs to activate solenoids and turn switches and lights on and off, or to interface the PDQ Board with a wide variety of digital accessories such as D/A converters, displays, etc.

A digital input allows the processor to monitor the logical state of an external voltage by reading a data register associated with the port. External voltages near 0 Volts connected to a digital input cause the corresponding bit in the port’s data register to be read as a logical 0, and external voltages near 5 Volts connected to a digital input are read as a logical 1. Application programs can use digital inputs to read switches and keypads or to interface to digital devices such as ATD converters and real-time clocks.

Using digital I/O is very easy: simply configure the output port as a digital input or output as explained below, and then use functions or assignment statements to read from or write to the port. The names of the data and direction registers and all required initialization routines are pre-defined in the header files so you don’t have to worry about hexadecimal register addresses in your code.

These register names enable use of the digital I/O ports:

Definitions of the register names in the above table can be found in the C Glossary; they are descriptive synonyms for the standard Motorola register names. Both the standard register names and the synonyms are declared in the C:\MosaicPlus\c\libraries\include\mosaic\HCS12REGS.h file. The synonyms are defined as follows:

// some digital i/o port synonyms (used in C glossary):
#define PORTJ              (PTJ)
#define PORTJ_DIRECTION    (DDRJ)
#define PORTM              (PTM)
#define PORTM_DIRECTION    (DDRM)
#define PORTP              (PTP)
#define PORTP_DIRECTION    (DDRP)
#define PORTP_IN           (PTIP)
#define PORTT              (PTT)
#define PORTT_DIRECTION    (DDRT)
#define PORTT_IN           (PTIT)
#define PORTAD0_MODE       (ATD0DIEN)
#define PORTAD1_MODE       (ATD1DIEN)
//  PORTAD0 and PORTAD1 are defined above;
//  they allow digital reads of A/D ports.

There are additional digital I/O port features that can be controlled via the registers listed in the following table. Each output pin can be configured to have reduced drive capability. Full-drive HCS12 pins configured as digital outputs in the high state can maintain the output voltage within 0.8 Volts of the positive supply if 10 mA or less is being drawn from the pin. In the low state, full-drive digital outputs can keep the voltage below 0.8 Volts while sinking up to 10 mA of current. Reduced drive pins can source or sink only 2 mA of current while staying within these voltage specifications. After a hardware reset, full drive is the default, and this is the recommended operating condition for most applications.

After a hardware reset, the available digital I/O pins on PORTM, PORTP, PORTT, and PORTJ come up as inputs with no pull-up or pull-down resistor. By writing a 1 to the corresponding bit in the Pull Enable Register as shown in the above table, a pull-up or pull-down is connected to the pin. If the Polarity Select Register bit contents equal 0 (the default after a reset), a pull-up is connected; otherwise, a pull-down is connected.

PORTP and PORTJ transitions can trigger an interrupt on the PORTP_ID and PORTJ_ID interrupt vectors, respectively. (PORTH transitions can also trigger interrupts on the PORTH_ID vector; this port is reserved to implement SPI1 and SPI2 for inter-processor communications). To enable interrupt generation by a specified pin or set of pins, set the corresponding bits in the interrupt enable register (PIEP for PORTP, PIEJ for PORTJ). An interrupt is triggered on an active edge, which is defined as a falling edge (the default) if the corresponding bit in the Polarity Select Register in the above table is 0, or a rising edge if the Polarity Select Register bit is 1. When an interrupt occurs, the flag bit of the pin that caused the interrupt is set in the interrupt flag register (PIEF for PORTP, PIEJ for PORTJ).

The following sub-sections describe how to configure and access the digital I/O ports on the PDQ Board. Subsequent chapters will describe how to use the alternate pin functions such as PWM outputs, output compares, input captures, pulse accumulators, and Analog To Digital converters.

As you work through the code examples in the remaining sections of the chapter, you can use a voltmeter to verify that the outputs are behaving as you expect. You can also connect the input signals through a 1 kOhm resistor to +5V or GND to verify that you can digitally read their values. The 1 kOhm resistor is just a safety precaution to minimize the chance that you’ll blow out a port bit by mistakenly connecting an output bit to a supply voltage; even if you make this mistake, the resistor would limit the current to safe levels.

PORTM is an 8-bit general purpose digital I/O port configurable as input or output on a bit-by-bit basis. PM0-5 are available on the Digital Field Header, and PM6 and PM7 are accessible on the Analog Field Header. To configure PORTM, use an assignment statement to write to the PORTM_DIRECTION register, also called the DDRM (Data Direction Register M) register. These and all of the HCS12 register names are defined in the HCS12REGS.h file in the C:\MosaicPlus\c\libraries\include\mosaic directory. Writing a 1 to a bit position in PORTM_DIRECTION configures the corresponding port bit as an output, and writing a 0 to a bit position configures the corresponding bit as an input. The default after a hardware reset is all inputs. For example, the following C statement configures PORTM as all outputs:

PORTM_DIRECTION = 0xFF;

To configure PORTM as all inputs, use the statement:

PORTM_DIRECTION = 0x00;

If we want to configure bits 0-6 as inputs, and bit 7 as output, we can execute:

PORTM_DIRECTION = 0x80;

To change the state of an output bit on PORTM, use an assignment statement with PORTM on the left hand side to write to the port’s data register named PORTM. For example, if PORTM is configured as all outputs, the following C statement sets all PORTM bits high:

PORTM = 0xFF;

To read the state of PORTM, use an assignment statement with PORTM on the right hand side to read the port’s data register. For example, the following code fragment reads PORTM and places the results in the variable named latest_portm_state:

static unsigned char latest_portm_state;
latest_portm_state = PORTM;

Because PORTM is not associated with a timer or PWM subsystem, the last value written to the register is typically the value present on the pins. This means that the PORTM register can be reliably used both for reading and writing, and use of the read-only PORM_IN register is not required.

PORTP is an 8-bit digital I/O port configurable as input or output on a bit-by-bit basis. The PP0-7 signals are available on the Digital Field Header on the PDQ Board. Any or all of the bits in PORTP can be configured as Pulse-Width Modulated (PWM) outputs under the control of the HCS12 processor’s PWM subsystem. After a hardware reset, PORTP is a digital input port with PWM disabled. The PWM drivers are explained in a later chapter. Briefly, the PWMEnable() function enables PWM control of a specified PORTP bit, and the PWMDisable() function disables PWM control of a specified bit. Both of these functions work by writing to the PWME (PWM Enable) register. In this section we assume that PWM control is disabled for all of the PORTP pins, allowing them to be used as standard digital I/O.

To configure PORTP, use an assignment statement to write to the PORTP_DIRECTION register, also called the DDRP (Data Direction Register P) register. These and all of the HCS12 register names are defined in the HCS12REGS.h file in the C:\MosaicPlus\c\libraries\include\mosaic\ directory. Writing a 1 to a bit position in PORTP_DIRECTION configures the corresponding port bit as an output, and writing a 0 to a bit position configures the corresponding bit as an input. The default after a hardware reset is all inputs. For example, the following C statement configures PORTP as all outputs:

PORTP_DIRECTION = 0xFF;

To configure PORTP as all inputs, use the statement:

PORTP_DIRECTION = 0x00;

If we want to configure bits 0-6 as inputs, and bit 7 as output, we can execute:

PORTP_DIRECTION = 0x80;

To change the state of an output bit on PORTP, use an assignment statement with PORTP on the left hand side to write to the port’s data register named PORTP. For example, if PORTP is configured as all outputs, the following C statement sets all PORTP bits high:

PORTP = 0xFF;

To read the state of PORTP, use an assignment statement with PORTP_IN on the right hand side to read the port’s data register. Reading PORTP may give incorrect results for any bits that are under PWM output control. Reading PORTP_IN returns the actual state of each pin, as opposed to the last value written to the PORTP register. For example, the following code fragment reads PORTP and places the results in the variable named latest_portp_state:

static unsigned char latest_portp_state;
latest_portp_state = PORTP_IN;

PORTT is an 8-bit digital I/O port configurable as input or output on a bit-by-bit basis. The PT0-7 signals are available on the Digital Field Header on the PDQ Board. Any or all of the bits in PORTT can be configured as timer-controlled I/O under the control of the processor’s Enhanced Capture/Timer (ECT) subsystem. After a hardware reset, PORTT is a digital input port with timer control disabled. The ECT software drivers are explained in a later chapter. The ECT system has many features, and there is a suite of functions that configure various timer actions on the PORTT pins. In this section we assume that ECT control is disabled for all of the PORTT pins, allowing them to be used as standard digital I/O.

To configure PORTT, use an assignment statement to write to the PORTT_DIRECTION register, also called the DDRT (Data Direction Register T) register. These and all of the HCS12 register names are defined in the HCS12REGS.h file in the C:\MosaicPlus\c\libraries\include\mosaic\ directory. Writing a 1 to a bit position in PORTT_DIRECTION configures the corresponding port bit as an output, and writing a 0 to a bit position configures the corresponding bit as an input. The default after a hardware reset is all inputs. For example, the following C statement configures PORTT as all outputs:

PORTT_DIRECTION = 0xFF;

To configure PORTT as all inputs, use the statement:

PORTT_DIRECTION = 0x00;

If we want to configure bits 0-6 as inputs, and bit 7 as output, we can execute:

PORTT_DIRECTION = 0x80;

To change the state of an output bit on PORTT, use an assignment statement with PORTT on the left hand side to write to the port’s data register named PORTT. For example, if PORTT is configured as all outputs, the following C statement sets all PORTT bits high:

PORTT = 0xFF;

To read the state of PORTT, use an assignment statement with PORTT_IN on the right hand side to read the port’s data register. Reading PORTT may give incorrect results for any bits that are under ECT (Enhanced Capture/Timer) output control. Reading PORTT_IN returns the actual state of each pin, as opposed to the last value written to the PORTT register. For example, the following code fragment reads PORTT and places the results in the variable named latest_portt_state:

static unsigned char latest_portt_state;
latest_portt_state = PORTT_IN;

PORTAD0 and PORTAD1 are each 8-signal analog or digital input ports; they cannot be configured as outputs. Analog inputs are controlled by the dual 8-channel ATD (Analog To Digital) subsystems on the HCS12 processor. PORTAD0 pins are named AN0-7, and PORTAD1 pins are named AN8-15; these 16 inputs are accessible on the Analog I/O header on the PDQ Board. To configure any or all of these lines as a digital input, create a 16-bit mask with a 1 in the bit position of each digital input, and pass the mask to the ATDDigitalInputs() function. ATDDigitalInputs() splits the 16-bit value into its 8-bit components and writes to the PORTAD0_MODE and PORTAD1_MODE registers (also called the ATD0DIEN and ATD1DIEN registers, respectively). If you prefer, you can configure specified pins as digital inputs by directly writing to the PORTAD0_MODE and PORTAD1_MODE registers. Both ports PORTAD0 and PORTAD1 are configured as analog inputs after a hardware reset; that is, the PORTAD0_MODE and PORTAD1_MODE registers equal 0 after a power-up or reset.

If a pin on one of these ports is configured as a digital input, it is important that your system not present an analog input to that pin. An analog input driving a pin configured as a digital input can put the pin electronics in an intermediate logic state that results in high currents inside the processor chip.

The ATD software drivers are explained in another chapter. In this section we assume that ATD inputs are disabled for all of the PORTAD0 and PORTAD1 pins, allowing them to be used as standard digital inputs. To configure the ports as digital inputs, execute:

ATDDigitalInputs( 0xFFFF );

As an alternative, you could execute the equivalent assignment statements:

PORT_AD0_MODE = 0xFF;
PORT_AD1_MODE = 0xFF;

These and all of the HCS12 register names are defined in the HCS12REGS.h file in the C:\MosaicPlus\c\libraries\include\mosaic\ directory. Writing a 1 to bit positions in PORTAD0_MODE configures the corresponding AN0-7 port bits as digital inputs, and writing a 0 to a bit positions configures the corresponding bits as analog inputs.

To read the digital state of the AN0-7 inputs associated with PORTAD0, use an assignment statement with PORTAD0 on the right hand side to read the port’s digital data register. For example, the following code fragment reads PORTAD0 and places the results in the variable named latest_portad0_state:

static unsigned char latest_portad0_state;
latest_portad0_state = PORTAD0;

Similarly, to read the digital state of the AN8-15 inputs associated with PORTAD1, use an assignment statement with PORTAD1 on the right hand side to read the port’s digital data register. For example, the following code fragment reads PORTAD1 and places the results in the variable named latest_portad1_state:

static unsigned char latest_portad1_state;
latest_portad1_state = PORTAD1;

PORTJ is a 4-bit multi-purpose digital I/O port. Bits PJ0 and PJ1 are reserved by the operating system to implement the transmit direction control for the RS485 driver chips of the serial1 and serial2 ports. Bits PJ2-5 are not implemented. Bit PJ6 implements the IIC (Inter-IC) serial bus SDA data line, and PJ7 implements the IIC SCL clock line; these lines are available on the PDQ Board’s analog field header. Each of these two IIC lines is conditioned with a 100 ohm series resistor and a nominal 5 Kohm pull-up resistor. If the IIC bus is not used, bits PJ6 and PJ7 can be configured for general purpose digital I/O. To configure PORTJ, use a read/modify/write assignment statement to write to bits 6 and 7 of the PORTJ_DIRECTION (also called DDRJ) register without modifying bits PJ0 or PJ1. These and all of the HCS12 register names are defined in the HCS12REGS.h file in the C:\MosaicPlus\c\libraries\include\mosaic\ directory. Writing a 1 to a bit position in PORTJ_DIRECTION configures the corresponding port bit as an output, and writing a 0 to a bit position configures the corresponding bit as an input. The default contents of PORTJ_DIRECTION after a hardware reset is 0x03: the RS485 transmit control signals on PJ0 and PJ1 are outputs, and the IIC signals on PJ6 and PJ7 are inputs. For example, the following C statement configures PJ6 and PJ7 as outputs:

PORTJ_DIRECTION |= 0xC0;

To configure PJ6 and PJ7 as inputs, use the statement:

PORTM_DIRECTION &= 0x3F;

To change the state of an bit PJ6 or PJ7 on PORTJ, use a read/modify/write statement such as |= or &= with PORTJ on the left hand side to write to the port’s data register named PORTJ. For example, if PJ6 and PJ7 are configured as outputs, the following C statement sets all PJ6 and PJ7 high:

PORTJ |= 0xC0;

Note that this statement does not change the state of PJ0 or PJ1, and so will not corrupt any in-process RS485 data transfers. To read the state of PORTJ, use an assignment statement with PORTJ on the right hand side to read the port’s data register. For example, the following code fragment reads PORTJ and places the results in the variable named latest_portj_state:

static unsigned char latest_portj_state;
latest_portj_state = PORTJ;

Care must be taken when performing read/modify/write operations in applications that use interrupts or multitasking. Operations such as setting or clearing individual bits in a byte while leaving other bits unchanged are called read/modify/write operations because they involve reading the port, modifying the read contents, and writing the result back to the port. Unpredictable results can occur if more than one interrupt service routine or task tries to access a single port or memory location at the same time using a read/modify/write sequence. The simplest solution to this problem is to access the memory location or port using an uninterruptable read/modify/write operator.

The following scenario illustrates the importance of uninterruptable operators when more than one task or interrupt routine is writing to a memory location. Let’s assume that two different tasks are controlling the bits of PORTM. Assume that TASK1 is controlling the state of bit PM4, and TASK2 controls bit PM7. Let’s assume that bit 4 is low when TASK2 tries to execute the following code:

static unsigned char mask = 0x80;
PORTM |= mask;

TASK2 is merely trying to set the top bit in PORTM to 1, but this statement may have unintended consequences. The compiler generates code that reads the contents of PORTM, performs a bitwise OR with the contents of mask, and stores the result back into PORTM. Assume that the timeslicer interrupt is serviced just after the OR instruction and transfers control to TASK1. TASK1 may change the state of bit PM4 to a 1. When control is then transferred back to TASK2, the final store to PORTM is executed. Unfortunately, this store command erroneously sets bit PM4 back to the low state! TASK2 was interrupted after it read the state of PORTM but before it had a chance to write the new contents, so it undoes the change that TASK1 made in the state of bit PM4! This can indeed cause problems in an application program.

The pre-coded read/modify/write functions avoid this problem by disabling interrupts for ten to thirteen processor cycles (0.5 to 0.65 microseconds). This prevents the corruption of the contents when different tasks or interrupts share access to a single location. The following functions are uninterruptable:

void  ChangeBits( uchar data, uchar mask, xaddr address )
void  ClearBits( uchar mask, xaddr address )
void  SetBits( uchar mask, xaddr address )
void  ToggleBits( uchar mask, xaddr address )
The following additional uninterruptable operators are declared in the MEMORY.h header file in the C:\MosaicPlus\c\libraries\include\mosaic\ directory:

void  StoreLongProtected  (long val,  xaddr address)
void  StoreFloatProtected (float val, xaddr address)
long  FetchLongProtected  (xaddr address)
float FetchFloatProtected (xaddr address)

These routines are described in detail in the C Glossary.

It is easy to create your own uninterruptable functions using the lock() and unlock() inline functions.

To use these handy utilities, declare inside your function a local unsigned char (8-bit) variable named prior_interrupt_state (or any appropriate name that you choose). Execute lock() and assign its 8-bit return value to prior_interrupt_state. This saves the prior interrupt state (globally enabled or globally disabled) and then globally disables interrupts by setting the I bit in the condition code register (CCR). Then you can perform any read/modify/write statements while interrupts are disabled. To return to the prior interrupt state, pass the prior_interrupt_state variable to restore() which restores the prior state of the I bit in the CCR.

For example, the following uninterruptable function sets specified bits in a port or memory byte:

void SetBitsUninterrupted( uchar mask, char* address )
{     unsigned char prior_interrupt_state;
      prior_interrupt_state = lock();
          // read/modify/write code goes here:
        *address |= mask;
      restore (prior_interrupt_state);
}

Simple stores to and fetches from 1-byte or 2-byte memory locations are intrinsically uninterruptable because they are implemented with single assembly-language opcodes. However, the HCS12 processor does not have a single opcode that can access a 32 bit memory location. Thus, problems can arise when one task writes to a floating point or long variable, and a second task needs to read the saved value. The data that is read may be invalid if the read or the write is interrupted between the time of the writing/reading of the first 16 bits and the writing/reading of the second 16 bits. In these cases uninterruptable operators such as should be used. An example is presented by the functions named:

void PokeFloatUninterrupted(float value, float* destination )
float PeekFloatUninterrupted(float *  source )

which are defined keyword in the TURNKEY.c example program found in the demo project called "Turnkey Demo".

The processor’s digital output pins are available for you to connect to external devices. You can use them to directly drive LEDs, relays, transistors, opto-isolators or other digital logic devices. But please be careful – whenever these outputs are connected to external devices you must stay within the voltage and current capabilities of the output pins.

The electrical characteristics of the processor’s digital I/O signals are specified in detail in Appendix A of the Motorola HCS12 Device Guide document. A table lists the 5V I/O Characteristics of the processor.

Pins on the HCS12 configured as digital inputs are guaranteed to report a logical high if the input voltage is greater than 0.65 times the supply voltage, or 3.25 Volts. They will always report a logical low if the input voltage is less than 0.35 times the supply voltage, or 1.75 Volt. Input voltages between 1.75 and 3.25 volts are indeterminate; they may be read as either high or low by the processor, depending on the exact value of the trigger, or threshold between logic high and logic low. The trigger voltage can lie anywhere within the 1.75 – 3.75 V gap, and is typically around 2.5V

Further, each input/output pin exhibits a little hysteresis provided by weak pullup and pulldown transistors on the input pins. The consequence of this hysteresis is that the threshold between a logic high and a logic low depends on whether the input voltage is rising or falling. The following diagram shows the measured threshold for a single pin.

The 0.14V gap between the rising and falling thresholds provides some noise immunity and prevents chatter on the pin during voltage transitions. When the input voltage rises from a logic 0 toward a logic 1 level, the logic 1 is recognized when the voltage rises to 2.582 volts. Negative going noise on the input voltage will not cause a false transition back to a logic 0 unless it is greater than 0.14V. Likewise, during a logic 1 to logic 0 transition, the input is protected against positive going noise spikes of less than 0.14V. The actual threshold values and degree of hysteresis will vary from pin to pin.

The hysteretic input works together with any source impedance driving the pin to provide some immunity against noise and to debounce the input signal.

Pins on the 9S12/HCS12 come up in the standard full drive mode, and can be configured for partial drive to save a small amount of bias current. Full drive mode is recommended for most applications. No action is required to obtain full drive, as this is the default condition after a reset.

Full-drive 9S12/HCS12 pins configured as digital outputs in the high state can maintain the output voltage within 0.8 V of the positive supply if 10 mA or less is being drawn from the pin. In the low state, full-drive digital outputs can keep the voltage below 0.8 V while sinking up to 10 mA of current. Load circuitry that requires significant current to be sourced or sunk by the digital output should include external resistors to ensure that the absolute maximum rating of 25 mA per output pin is never exceeded.

These digital output pins are very useful because they can directly drive a wide range of devices. Nevertheless, any circuitry connected to the processor should take care to:

• Prevent excessive voltage levels at the pin; and,
• Prevent excessively great currents.

We’ll address each of these concerns in turn.

Excessive voltages are prevented by ensuring that voltages of less than a diode drop below V_SS (that is, -0.6 V below ground) or greater than a diode drop above V_DD (that is, 5.0 + 0.6 V) are never applied to the processor. For some applications, particularly when driving inductive loads such as relays, you may need to provide Schottky diode clamps between the pin and V_DD and between the pin and ground. All digital I/O pins on the processor have inherent diode clamps to the processor’s ground voltage, V_SS, but it is best not to rely on these. If there is the possibility of the output pin being driven to a negative voltage level it is better to prevent excessive power dissipation in the processor package by externally clamping the voltage to ground (V_SS) with a Schottky diode.

The current into or out of any pin on the MCHCS12 should also be limited to prevent damage. The specified maximum instantaneous current is 25 mA into or out of any one pin at a time. In driving more than one pin at a time it is necessary to stay within the processor’s maximum power dissipation. Unfortunately, Motorola doesn’t specify exactly what this maximum is, but we recommend that you don’t exceed a total of 250 mW for all processor I/O pins combined if you are operating within the commercial temperature range (0 to 70 degrees centigrade). The chip’s total power dissipation is the sum of its internal power (which varies from device to device so much that it can only be determined by actually measuring it, but which is specified at less than 325 mW) and the power associated with the I/O pins. Pin currents must be limited using external resistors.

The output pins of the HCS12/9S12 are similar in electrical characteristics to the SN54/74HC digital logic family. The digital outputs can source or sink up to 25 mA, although they are specified at ±10mA. A valid logic high level is between V_OH = V_DD and V_OH = 0.65 V_DD, and a valid low level is between V_OL =V_SS = 0 V and V_OL =V_SS + 0.35 V_DD. As the output is loaded, the V_OL and V_OH levels rise or fall. It is often useful to know just how much to expect the V_OL and V_OH levels to degrade with current.

When the pins are operated with full drive capability (their default state) their output resistance is approximately 40Ω. That is, for currents of less than 10 mA the voltage change is linear with current; it can be modeled as a voltage source of either zero or five volts and an equivalent series resistance of 40 ohms ¹⁾. At greater output currents the resistance increases gradually, but the 40 ohm approximation holds good up through the 25 mA maximum. At this current the voltage degradation of the V_OL or V_OH is about 1 volt. The following graphs illustrate the variation.

The graphs (or the simpler 40Ω value) can be used to choose component values for particular circuits. For example if we wish to use an I/O pin to drive a light-emitting diode, we would place the LED in series with a resistor and connect them between an output pin and ground. The resistor limits the current into the LED. From the LED datasheet we note that its forward voltage at a current of 10 mA is specified to be 2.2 V. What should the resistor value be? We calculate it as,

  R = (V_OH - 2.2 V ) / 10 mA

Consulting the V_OH vs I curve for the I/O pin, we find that V_OH = 4.6 V at 10 mA. Plugging 4.6V into the above equation results in a calculated external resistance of 240 ohms.

You may either source current to the LED, or sink current from it, as shown in the following circuit. When sourcing current to it an active high turns ON the LED; when sinking current an active low turns ON the LED.

The following graphs show that the resistance of an output pin in either the high or low state is approximately 40 ohms for currents to the maximum of 25 mA.

The following graphs show that in reduced drive mode the resistance of an output pin is approximately 200 ohms in either the high or low state.

See also → Pulse Width Modulated I/O