Appendix A - QED Board Memory Map

The QED Board increases the 68HC11's 64K memory space to 8 Megabytes. This is accomplished by designating an 8-bit port on the processor (Port G) as a "page latch" that provides 8 additional address lines.

A memory map is a diagram of how the memory is allocated to various tasks and services. As pictured in the memory map of Figure A.1, the bottom 32K of the processor's address space at addresses 0000-7FFF_H is "paged memory", and the page latch allows up to 256 pages of memory to be selected (256 pages X 32Kbytes/page = 8 Megabytes of memory). The page latch is used to select which memory device is active, and the processor's address lines are used to address a particular location within the selected memory device.

The top 32K of the 68HC11's memory at addresses 8000_H-FFFF_H is called the "common memory"; it is always accessible regardless of the contents of the page latch. The most frequently called kernel routines as well as the stacks and user area reside in the common memory, and so are accessible without a page-change operation. Most words call either kernel routines or other words compiled on the same page as the calling word. The result is that very few page changes are needed when running a program, and this maximizes execution speed.

In most cases, the programmer need not worry about the details of using paged memory. The QED-Forth compiler automatically compiles page-change operations into definitions when they are needed. The basic memory operations are all smart enough to know how to handle the paged memory. The QED-Forth memory operations (for fetching, storing, moving memory, performing address calculations, and managing the heap memory) treat the paged memory as a single contiguous area. As suggested by the connecting arrows in the Figure A.1, the memory operations know that the last address (7FFF_H) on any page is followed immediately by the first location (0000) on the next page. This contiguous memory allows very large data structures such as arrays and matrices to be used.

Only three basic compiler operations do not allow a page boundary to be crossed: compiling a single header, compiling a definition, and allotting a parameter field for a variable or data structure (array, matrix, etc.). In each of these cases, the programmer is alerted if there is a problem by a clearly stated error message. For example, assume that the dictionary pointer DP contains the extended address 7FFE_H\4 which is almost at the top of page 4. Attempting to compile a new definition at this point would result in an error message stating that a page boundary was crossed. To solve this problem, simply set DP to point to more available memory (for example, address 0000 on page 5), re-compile the definition, and continue compiling. Likewise, if the name pointer NP or the variable pointer VP have been incremented during compilation so that they are about to overflow a page boundary, you may receive an error message that prompts you to explicitly reset the offending pointer to point to available RAM before continuing with compilation.

Of course, definitions may contain calls to routines that are on other pages, so long as each definition is on a single page. Likewise, the linked list of names may flow across many pages, so long as each individual header is on a single page. In practice, these restrictions pose almost no limitation to the performance or ease of use of QED-Forth.

The full-page memory map in Figure A.1 details the allocation of the memory on the QED Board. The QED Board has 3 memory sockets labeled S1, S2, and S3. Each can accommodate a memory device ranging from 32 Kbytes to 128 Kbytes.

Socket S1 is next to the 34-pin keypad/display header. It accommodates the 64K QED-Forth ROM which holds the development system as well as the runtime libraries. This ROM must be present for the QED Board to function. The kernel occupies 32K at addresses 0000_H-7FFF_H on page 0, 19K at B400_H-FFFF_H in common memory, and 12K at addresses 0000_H-2FFF_H on page fifteen (0FH). In the future up to 64K additional kernel memory may be added on pages 12 and 13.

Socket S2 (the center socket) holds a 32K or 128K RAM, and at least 32K of RAM must be present in this socket for the QED Board to operate. This memory cannot be write-protected. If a 32K RAM is installed, the onboard logic places 20K of it on page fifteen (0FH) at addresses 3000_H to 7FFF_H and the remainder is common RAM. Some common RAM is reserved by QED-Forth, and some is overmapped by the 68HC11's EEPROM. 11.5K of common RAM remains available to the programmer at addresses 8400_H-ADFF_H and B000_H-B3FF_H. If a 128K RAM is installed in socket S2, the three 32K pages numbered 1, 2, and 3 are also available.

Socket S3 is called the "RAM/ROM socket", located near the 10-pin serial connector. It accommodates either RAM (typically during program development) or PROM (typically in your final product). During program development and debugging, a 128K battery-backed RAM is typically installed in this socket. The memory is addressed at pages 4, 5, 6, and 7, and each page contains 32 Kbytes. Turning DIP switch #1 ON write-protects pages 4 and 5, and turning DIP switch #2 ON write-protects pages 6 and 7. This socket is an ideal location for the memory areas such as the definitions and name areas that will end up as PROM in the final system. During program development, code can be compiled into RAM in this socket, and the memory can be write-protected to emulate a PROM. When the application is completely debugged, the contents can be burned into a PROM, and the PROM can be plugged into the same socket. Turning dip switch #3 ON configures the socket to accommodate a PROM. The PROM size can be 32K (page 4 only), 64K (pages 4 and 5), or 128K (pages 4, 5, 6, and 7).

Two of the DIP switches on the board can be used to write protect various pages of memory. Write-protected battery-backed memory holds its data even when the board is powered down, and cannot be modified by the processor. Thus it behaves as "emulated ROM". Pages 4 and 5 become write-protected emulated ROM (that is, the contents cannot be modified) when DIP switch 1 is in the ON position, and are modifiable RAM when switch 1 is in the OFF position. Similarly, pages 6 and 7 are write-protected when switch 2 is in the ON position and are RAM when switch 2 is in the OFF position. Using these write-protection switches eliminates the need for PROM burning during program development.

As described in the chapter titled "Memory Mapped I/O and the Prototyping Board" in the QED Hardware Manual, it is easy to add memory-mapped I/O peripherals as well as additional memory to the system. Peripherals can be mapped onto any unused page. It is suggested that, if appropriate for your application, you reserve the top 16 pages of memory, pages 240-255, for add-on boards to the QED system. Future peripheral boards produced by Mosaic Industries will be addressable at any of the top 16 pages.

Alternatively, peripherals that must be accessed very rapidly without changing pages can be mapped into the reserved 128-byte region at addresses C000Usub>H</sub>-C07F_H in common memory. Note that the memory bus signal /OE (active-low output enable) is not active in this region. The hardware manual details how to add page-mapped and common-memory-mapped peripherals.