Table of Contents
UART Wildcard User Guide
The UART Wildcard implements two full-duplex serial ports that can be configured for RS232, RS422, and RS485 protocols. This tiny 2" by 2.5" board is a member of the WildcardTM series that connects to Mosaic controllers.
This document describes the capabilities of the UART Wildcard, tells how to configure the hardware, and presents an overview of the driver software. A glossary of the software device driver functions, demonstration program source code, and complete hardware schematics are included.
A "UART" is a "Universal Asynchronous Receiver/Transmitter" that converts parallel data from the host processor (any Mosaic controller) into a serial data stream. Each of the two UARTs on the wildcard is capable of "full duplex" communications, meaning that both transmission and reception can occur simultaneously (although the RS485 protocol is half duplex as explained below). In other words, each "local" UART on the wildcard can both send data to and receive data from a "remote" UART on the other end of a connecting serial cable. The local and remote must share a common ground, so all serial cables include at least one ground conductor. The words "port" and "channel" are used interchangeably to refer to a serial communications link.
The serial interface is asynchronous, meaning that there is no clock transmitted along with the data. Rather, the transmitter and receiver must be communicating using a known "baud rate", or bit frequency. Both the local and remote UARTs must be configured for the same baud rate. Software-selectable baud rates up to 56,000 baud are supported. Standard attainable baud rates are 300, 1200, 2400, 4800, 9600, 19200, 38400 and 56000 baud.
Serial data is shifted out least-significant-bit first. At the UART, a logic high (5 volts) is called a "mark", and a logic low (0 volts) is called a "space". The serial output at the UART idles at the logic high (mark) level. A logic-low "start bit" marks the start of a character, followed by 5 to 8 data bits per character. An optional "parity" bit can be specified to enable error detection by the UART. One to two logic-high "stop bits" mark the end of a character.
Parity options include even, odd, high, low, or no parity. Even parity means that the bits sum to an even number, and odd parity means that the bits sum to an odd number. High (mark) parity means that the parity bit is always logic 1 at the UART, and low (space) parity means that the parity bit is always logic 0 at the UART. No parity means that there is no parity bit.
A "break" sequence forces the serial output to a logic low (space) at the UART. Both the local and remote UARTs must be configured for the same communications parameters. The standard data format for the QED product line is 8 data bits, no parity, and 1 stop bit.
Each UART implements transmit and receive "FIFO" buffers to reduce the required frequency of service by the host processor. A FIFO is a First In/First Out buffer that can queue a burst of outgoing characters for transmission, or save a set of incoming characters until the host can read them. Each of the two channels on the UART Module implements two 16-character FIFOs, one for outgoing characters and one for incoming characters.
Serial Driver Chips
The serial data stream at the UART is conditioned by serial driver chips that transmit and receive the data. The resulting signal levels on the interface cable connect the local and remote in a manner specified by a standard "protocol". The most widely used protocol is RS232, a full duplex protocol with a single-ended bipolar voltage swing on the serial cable. Newer protocols include the full duplex RS422 and the half duplex RS485 protocols, each of which drives differential 0 to 5 volt signals on the serial cable.
Each of the two channels on the UART module can be configured for RS232, RS422, or RS485. The protocols are described in turn.
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