Table of Contents
24/7 Data Acquisition Wildcard Users Guide
Once the 24/7 Data Acquisition Wildcard has been initialized, calibrated, and configured, you can take one or more samples using AD24_Sample or AD24_Multiple. Irrespective of the resolution option chosen, the samples are returned as 32-bit (4 byte) values. AD24_Sample acquires a single sample by polling the analog to digital converter. If a sample is not available within a timeout period, an error is returned. The timeout period is calculated by Equation 3.
Equation 3: Calculation of the Timout Value
The calibration delay is based on the calibration option and is listed in Table 4 as the "Duration of Calibration". The timeout period allowed is always great enough to account for the filter settling time (pipeline delay) after a channel is changed. If a timeout occurs, the timeout error flag is placed in the least significant byte of the returned 32-bit value. A 32-bit value is used to allow an error flag to be returned with data regardless of the resolution (16 or 24 bits). See Figure 3 for a diagram of the data format.
WWWWWWWW XXXXXXXX YYYYYYYY ZZZZZZZZ
Figure 3: 32 Bit Value Returned By AD24_Sample
For a 16 bit sample, WWWWWWWW is the most significant byte, XXXXXXXX is the least significant byte, YYYYYYYY is 0, and ZZZZZZZZ is the timeout flag. For a 24 bit sample, WWWWWWWW is the most significant byte, XXXXXXXX is the next significant byte, YYYYYYYY is the least significant byte, and ZZZZZZZZ is the timeout flag.
To obtain multiple samples, you can use AD24_Multiple. This routine acquires up to 8192 samples and stores the samples as sequential 32 bit values in memory within a timeout period or a false flag is returned. This routine sets up an interrupt service routine to obtain the multiple samples. The interrupt service routine (ISR) runs at more than twice the sample frequency to eliminate clock variations between the 24/7 Data Acquisition Wildcard and the controller board and to guarantee that a sample is not missed even if the ISR is delayed up to 1/2 a sample period (or one full ISR period). Equation 4 shows how the ISR period is calculated.
Equation 4: Calculation of the ISR Period
The interrupt latency delay is composed of 200 μs for the time to update the analog to digital converter’s data register with sample values, 10 μs of interrupt latency delay, and 50 μs to read the data ready line when the ISR is entered. You can also use this equation to calculate the maximum time the ISR can be delayed or the SPI used without missing a sample. The 24/7 Data Acquisition Wildcard uses the SPI to communicate with the controller board. You can create other tasks or routines that use the SPI as long as they do not use the SPI longer than one ISR period. For example to guarantee that a sample is not missed at a sample rate of 10 Hz, the maximum time another interrupt can take or routine can use the SPI is approximately 50 ms (0.04987 = ((1/10) - 0.00026) / 2).
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