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I2C Bus Electrical Specifications
The cable length limit for an I²C (IIC or I2C) serial bus is inversely proportional to the bus speed or clock rate

Every communication system has its own scope, and the I2C specification targets multi-drop, short range wired communication. It is ideally suited to communication between ICs on a printed circuit board, or communication between a processor board and nearby sensors where there is little cable capacitance. The lower the bus speed, the more cable capacitance that can be tolerated, and the longer the cable limit. Higher bus speeds require shorter cables.


I2C maximum cable length
I2C transmission distance, data rate, cable capacitance, and cable length limit

Devices on an I2C bus use open drain (or open collector) pins. Bus signals are actively pulled down by the communicating devices, but they are only passively pulled up by the pull-up resistors on each line. Consequently, the rate of a voltage transition from a logic low to high depends on the resistance value and the capacitance of the signal line. Figure 1 shows multiple devices attached to a single I2C bus.

Diagram of the two wire I2C bus showing passive pull-up.
Fig. 1  The two wire open-drain I2C bus relies on pull-up resistors to return its data (SDA) and clock (SCL) lines to their inactive (high) signal levels.

For a given data rate, the maximum number of devices on the bus is limited by the capacitance on the SDA and SCL pins, and is also a function of the pull-up resistance values on the SDA and SCL lines. 4.7 Kohm pull-ups are installed on the SDA and SCL lines on the PDQ Board. Using the default pull-up values, the PDQ Board’s I2C port is capable of data transfer rates up to 100 kilobits per second with maximum bus loading of 170 picofarads (pF). Adding parallel 3.3K resistors to the SDA and SCL lines brings the equivalent pull-up resistance down to 2K, and allows 100 KHz signaling with bus capacitance as high as 400 pF. The HCS12 MCU can generate data rates up to 1 megabit per second, but accurate data exchange at these high rates requires very low bus loading (say, under 40 pF with 2K pull-ups). Lowering capacitive loading to these levels is difficult, and requires short cable lengths and very few peripheral devices on the I2C bus.

Cable capacitance
For reference, shielded 22 AWG twisted pair cables have capacitance in the range of 100-240 pF/m. So the maximum bus length of an I2C link is about 1 meter at 100 Kbaud, or 10 meters at 10 Kbaud. Unshielded cable typically has much less capacitance, but should only be used within an otherwise shielded enclosure.

Alternate uses for the I2C I/O pins
PORTJ pins 6 and 7 may be used as general I/O pins

If the I2C bus is not needed, the associated HCS12 pins (PORTJ pins 6 and 7) can be configured as general purpose digital I/O , but note that the PJ6 (SDA) and PJ7 (SCL) signals are conditioned with 4.7K pull-up and 100 ohm series resistors.


To learn more about I2C specifications

This page is about: I2C Bus Range and Electrical Specifications, Freescale 9S12 HCS12 MC9S12 I2C Hardware – The I2C (IIC, Inter-IC) bus hardware interface of the Freeescale 9S12 HCS12 MC9S12 is intended for short range inter-chip communications. There is a cable length limit: reliable transmission distance is determined by a trade-off between data rate, cable length/capacitance, pull up resistance, drive capability and transmitter and receiver electrical specifications. Freescale MCU I2C interface, I2C bus, I2C spec, I2C specification, I2C protocol, IIC bus, I2C data frame, I2C error handling, I2C electrical specifications, I2C application note, using I2C, I2C interrupt service routine, I2C ISR, I2C open drain bus, IIC open collector bus