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Appendix A - QED Board Memory Map

8 Megabyte Address Space

The QED Board increases the 68HC11's 64K memory space to 8 Megabytes. This is accomplished by designating an 8-bit port on the processor (Port G) as a "page latch" that provides 8 additional address lines.

A memory map is a diagram of how the memory is allocated to various tasks and services. As pictured in the memory map of Figure A.1, the bottom 32K of the processor's address space at addresses 0000-7FFFH is "paged memory", and the page latch allows up to 256 pages of memory to be selected (256 pages X 32Kbytes/page = 8 Megabytes of memory). The page latch is used to select which memory device is active, and the processor's address lines are used to address a particular location within the selected memory device.

The top 32K of the 68HC11's memory at addresses 8000H-FFFFH is called the "common memory"; it is always accessible regardless of the contents of the page latch. The most frequently called kernel routines as well as the stacks and user area reside in the common memory, and so are accessible without a page-change operation. Most words call either kernel routines or other words compiled on the same page as the calling word. The result is that very few page changes are needed when running a program, and this maximizes execution speed.

 

QED-Forth Handles the Details of Paged Memory

In most cases, the programmer need not worry about the details of using paged memory. The QED-Forth compiler automatically compiles page-change operations into definitions when they are needed. The basic memory operations are all smart enough to know how to handle the paged memory. The QED-Forth memory operations (for fetching, storing, moving memory, performing address calculations, and managing the heap memory) treat the paged memory as a single contiguous area. As suggested by the connecting arrows in the Figure A.1, the memory operations know that the last address (7FFFH) on any page is followed immediately by the first location (0000) on the next page. This contiguous memory allows very large data structures such as arrays and matrices to be used.

Only three basic compiler operations do not allow a page boundary to be crossed: compiling a single header, compiling a definition, and allotting a parameter field for a variable or data structure (array, matrix, etc.). In each of these cases, the programmer is alerted if there is a problem by a clearly stated error message. For example, assume that the dictionary pointer DP contains the extended address 7FFEH\4 which is almost at the top of page 4. Attempting to compile a new definition at this point would result in an error message stating that a page boundary was crossed. To solve this problem, simply set DP to point to more available memory (for example, address 0000 on page 5), re-compile the definition, and continue compiling. Likewise, if the name pointer NP or the variable pointer VP have been incremented during compilation so that they are about to overflow a page boundary, you may receive an error message that prompts you to explicitly reset the offending pointer to point to available RAM before continuing with compilation.

Of course, definitions may contain calls to routines that are on other pages, so long as each definition is on a single page. Likewise, the linked list of names may flow across many pages, so long as each individual header is on a single page. In practice, these restrictions pose almost no limitation to the performance or ease of use of QED-Forth.

 

Available PROM and RAM on the QED Board

The full-page memory map in Figure A.1 details the allocation of the memory on the QED Board. The QED Board has 3 memory sockets labeled S1, S2, and S3. Each can accommodate a memory device ranging from 32 Kbytes to 128 Kbytes.

Socket S1 is next to the 34-pin keypad/display header. It accommodates the 64K QED-Forth ROM which holds the development system as well as the runtime libraries. This ROM must be present for the QED Board to function. The kernel occupies 32K at addresses 0000H-7FFFH on page 0, 19K at B400H-FFFFH in common memory, and 12K at addresses 0000H-2FFFH on page fifteen (0FH). In the future up to 64K additional kernel memory may be added on pages 12 and 13.

Socket S2 (the center socket) holds a 32K or 128K RAM, and at least 32K of RAM must be present in this socket for the QED Board to operate. This memory cannot be write-protected. If a 32K RAM is installed, the onboard logic places 20K of it on page fifteen (0FH) at addresses 3000H to 7FFFH and the remainder is common RAM. Some common RAM is reserved by QED-Forth, and some is overmapped by the 68HC11's EEPROM. 11.5K of common RAM remains available to the programmer at addresses 8400H-ADFFH and B000H-B3FFH. If a 128K RAM is installed in socket S2, the three 32K pages numbered 1, 2, and 3 are also available.

Socket S3 is called the "RAM/ROM socket", located near the 10-pin serial connector. It accommodates either RAM (typically during program development) or PROM (typically in your final product). During program development and debugging, a 128K battery-backed RAM is typically installed in this socket. The memory is addressed at pages 4, 5, 6, and 7, and each page contains 32 Kbytes. Turning DIP switch #1 ON write-protects pages 4 and 5, and turning DIP switch #2 ON write-protects pages 6 and 7. This socket is an ideal location for the memory areas such as the definitions and name areas that will end up as PROM in the final system. During program development, code can be compiled into RAM in this socket, and the memory can be write-protected to emulate a PROM. When the application is completely debugged, the contents can be burned into a PROM, and the PROM can be plugged into the same socket. Turning dip switch #3 ON configures the socket to accommodate a PROM. The PROM size can be 32K (page 4 only), 64K (pages 4 and 5), or 128K (pages 4, 5, 6, and 7).

 

Write-Protecting the Battery-Backed RAM

Two of the DIP switches on the board can be used to write protect various pages of memory. Write-protected battery-backed memory holds its data even when the board is powered down, and cannot be modified by the processor. Thus it behaves as "emulated ROM". Pages 4 and 5 become write-protected emulated ROM (that is, the contents cannot be modified) when DIP switch 1 is in the ON position, and are modifiable RAM when switch 1 is in the OFF position. Similarly, pages 6 and 7 are write-protected when switch 2 is in the ON position and are RAM when switch 2 is in the OFF position. Using these write-protection switches eliminates the need for PROM burning during program development.

 

Adding Memory Mapped Peripherals

As described in the chapter titled "Memory Mapped I/O and the Prototyping Board" in the QED Hardware Manual, it is easy to add memory-mapped I/O peripherals as well as additional memory to the system. Peripherals can be mapped onto any unused page. It is suggested that, if appropriate for your application, you reserve the top 16 pages of memory, pages 240-255, for add-on boards to the QED system. Future peripheral boards produced by Mosaic Industries will be addressable at any of the top 16 pages.

Alternatively, peripherals that must be accessed very rapidly without changing pages can be mapped into the reserved 128-byte region at addresses C000Usub>H</sub>-C07FH in common memory. Note that the memory bus signal /OE (active-low output enable) is not active in this region. The hardware manual details how to add page-mapped and common-memory-mapped peripherals.

 

QED Board Memory Map Description

Address Range (hex) Page (decimal) Function
0000 - 7FFF 0 QED-Forth Kernel; ROM.
0000 - 7FFF 1 Page 1. This 32K RAM page may be used freely for programs and data. Available if a 128K RAM is present in socket S2 (the center socket). Cannot be write-protected.
0000 - 7FFF 2 Page 2. This 32K RAM page may be used freely for programs and data. Available if a 128K RAM is present in socket S2 (the center socket). Cannot be write-protected.
0000 - 7FFF 3 Page 3. This 32K RAM page may be used freely for programs and data. Available if a 128K RAM is present in socket S2 (the center socket). Cannot be write-protected.
0000 - 7FFF 4 Page 4. This 32K battery backed RAM/PROM page may be used freely for programs and data. Available if a 32K or larger memory device is present in socket S3 (the RAM/PROM socket nearest to the serial connector). Can be write-protected by turning DIP switch#1 ON. Accommodates PROM if DIP switch#3 is ON.
7FFA - 7FFF 4 PRIORITY.AUTOSTART VECTOR. This address is the first of six locations whose contents indicate whether a PROM-based autostart word should be executed on start up. Beginning at 7FFA, storing the pattern 1357H followed by a word's extended code field address (xcfa), will cause the word to be executed upon subsequent restarts. Initialized by PRIORITY.AUTOSTART. See also addresses AE00-AE05 in common memory which are initialized by AUTOSTART.
0000 - 7FFF 5 Page 5. This 32K battery backed RAM/PROM page may be used freely for programs and data. Available if a 64K or larger memory device is present in socket S3 (the RAM/PROM socket nearest to the serial connector). Can be write-protected by turning DIP switch#1 ON. Accommodates PROM if DIP switch#3 is ON.
0000 - 7FFF 6 Page 6. This 32K battery backed RAM/PROM page may be used freely for programs and data. Available if a 128K memory device is present in socket S3 (the RAM/PROM socket nearest to the serial connector). Can be write-protected by turning DIP switch#2 ON. Accommodates PROM if DIP switch#3 is ON.
0000 - 7FFF 7 Page 7. This 32K battery backed RAM/PROM page may be used freely for programs and data. Available if a 128K memory device is present in socket S3 (the RAM/PROM socket nearest to the serial connector). Can be write-protected by turning DIP switch#2 ON. Accommodates PROM if DIP switch#3 is ON.
0000 - 7FFF 12 Page twelve (CH). Reserved for future kernel expansion. Available if a 128K ROM is present in socket S1 (the QED-Forth Kernel ROM socket next to the keypad/display connector).
0000 - 7FFF 13 Page thirteen (DH). Reserved for future kernel expansion. Available if a 128K ROM is present in socket S1 (the QED-Forth Kernel ROM socket next to the keypad/display connector).
0000 - 7FFF 14 Page fourteen (EH). Reserved for future kernel expansion.
0000 - 2FFF 15 Bottom 12K of page fifteen (FH) holds QED-Forth Headers; ROM.
3000 - 7FFF 15 Top 20K of page fifteen (FH) is RAM that may be used freely for program development and data. Available as long as the required 32K or larger RAM is present in socket S2. Cannot be write-protected.
0000 - 7FFF 224-255 Top 32 pages of memory. If you expect to add memory mapped peripheral cards to your system, we suggest that you reserve these pages for them. The QED prototyping board provides decoded chip select signals for these pages.
8000 - 807F Common CPU CONTROL AND STATUS REGISTERS. These registers configure the CPU and its peripheral subsystems. They also provide an interface to the 68HC11F1's I/O ports.
8080 - 80BF Common PIA CONTROL REGISTERS. These registers are used to configure and control three general purpose I/O ports. They are named PPA, PPB, and PPC.
8080 Common PPA, PIA I/O port A.
8081 Common PPB, PIA I/O port B.
8082 Common PPC, PIA I/O port C.
8083 Common PIA control/configuration register.
80C0 - 80FF Common Chip select address for 8-bit digital to analog converter.
8100 - 83FF Common RESERVED FOR SYSTEM USE. (Multitasker control variables,
8100 - 814F Common Serial2 receive buffer, holds 80 characters.
8150 - 819F Common Serial2 transmit buffer, holds 80 characters.
81A0 - 81EF Common LCD display buffer, holds 80 characters.
8200 Common UP. The user pointer holds the 16-bit base address of the current task's user area.
8400 - 95FF Common DEFAULT COMMON RAM MAP. After a COLD restart QED-Forth allocates its stacks, TIB, POCKET, PAD, HEAP, and variable area to reside in this 4.5K area of common RAM. All of these memory areas except the default user area at 8400 may be moved to meet the requirements of the application program. The default locations are listed here.
8400 Common USER.START. Start of the 1/4K user area for the startup task.
8800 Common RSTACK.START. The return stack starts here and grows downward in memory. 3/4K is allocated.
8B00 Common DSTACK.START. The data stack starts here and grows downward in memory. 3/4K is allocated.
8B00 Common TIB.START. Start address of the TIB. 96 bytes are allocated, limiting character line lengths to 96 characters unless the TIB is resized.
8B60 Common POCKET.START. Start address of the POCKET buffer used by WORD. 36 bytes are allocated.
8BA8 Common PAD.START. Start address of PAD. 36 bytes are allocated below PAD for numeric conversion, and 88 bytes are allocated above PAD as a scratchpad available for use by the application program.
8C00 Common HEAP.START. Address of the first byte in the default heap which has a size of 1/2 K.
8DFF Common HEAP.END. Address of the last byte in the default heap.
8E00 Common VARIABLE.START. Start of the variable area. 1/2K of memory space is allocated.
9000 Common NAME.AREA.START. Start of the name area of the dictionary where headers are stored. 1/2K is allocated.
9200 Common DEFINITON.AREA.START. Start of the definitions area of the dictionary. 1K is allocated.
9600 - ADFF Common 6K AVAILABLE RAM. This memory may be used for any purpose (large stacks, variable space, task areas, etc.)
AE00 - AEBF Common RESERVED EEPROM. This 192 bytes of EEPROM memory is used by QED-Forth for revectoring interrupt handlers and specifying user-defined configuration options. These EEPROM cells may be carefully used for other purposes if the application program does not need the features associated with the reserved bytes. The functions of the reserved bytes are specified below.
AE00 Common AUTOSTART VECTOR. This address is the first of six locations whose contents indicate whether an EEPROM-based autostart word should be executed on start up. Beginning at AE00, storing the pattern 1357H followed by a word's extended code field address (xcfa), will cause the word to be executed upon subsequent restarts. Initialized by AUTOSTART. See also addresses 7FFA-7FFF on page 4 which are initialized by PRIORITY.AUTOSTART.
AE06-AE0B Common PROTECTED REGISTER INITIALIZATION. If AE06 contains the pattern 13H then the 5 bytes at AE07-AE0B contain the specified contents that will be written into the protected registers INIT, OPTION, TMSK2, BPROT, and BAUD upon subsequent resets. This area is initialized by INSTALL.REGISTER.INITS.
AE0C-AE1A Common SAVE and RESTORE Parameter Area. Holds the memory map parameters used by SAVE and RESTORE.
AE1B Common INIT.VITAL.IRQS.ON.COLD flag. A flag is stored in AE1B indicating whether a vital interrupt vectors should be initialized upon a COLD reset.
AE1C Common DO.COLD.ON.RESET flag. A flag is stored in AE1C indicating whether a COLD should be performed on all resets.
AE1D Common INIT.SERIAL2.AT.STARTUP flag. A flag is stored in AE1D indicating whether a the secondary serial port should be used by QED-Forth upon each restart. The flag equals the specified serial baud rate divided by 75.
AE1E - AE1F Common Reserved for future use.
AE20 - AEBF Common INTERRUPT VECTORS. Each of 20 interrupts is allocated 8 bytes which are initialized as specified by an ATTACH instruction. If necessary, the EEPROM bytes associated with unused interrupts may be carefully used for other purposes.
AEC0 - AFFF Common AVAILABLE EEPROM. This 320 bytes of EEPROM may be freely used by application software.
B000 - B3EF Common 1K AVAILABLE ON-CHIP RAM. This 1K memory is not battery backed and resides internally in the 68HC11F1. It may be freely used by application software.
B3F0 - B3FF Common RESERVED FOR REAL-TIME CLOCK. This 16-byte buffer may be used for other purposes if the "smartwatch" real-time clock is not installed in socket S2 (the center memory socket).
B400 - BFFF Common QED-Forth Kernel; ROM.
C000 - C07F Common 128 byte "notch" that is available for memory mapped peripherals and I/O. Devices mapped here can be accessed quickly without a page change.
C080 - FFFF Common QED-Forth Kernel; ROM.
 
This page is about: Microcontroller and Single Board Computer Memory Allocation – 8 Megabyte Address Space The QED Board increases 68HC11s 64K memory space to 8 Megabytes. This is accomplished by designating an 8 bit port on processor (Port G) as page latch that provides 8 additional address lines. A memory map is diagram of how …
 
 
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