\ ---------------------------------------------------------------------
\ AUTHOR:      DAVID J. SIU
\ DATE:        8/30/2001
\ VERSION:     8.00
\ ---------------------------------------------------------------------
\ This is the driver code for Analog Devices 24 bit sigma delta A/D.
\ ---------------------------------------------------------------------
\ High Level User Words:
\   Init_AD24 ( module_number\base_xaddr -- success )        
\     - Initializes A/D Module by setting up CPLD and resetting AD7714.
\   Reset_AD24 ( -- )
\     - Resets all logic, the digital filter and the analog modulator 
\       while all on-chip registers are reset to thier default state.  
\   Software_Reset ( -- )
\     - Resets serial interface but not the contents of any registers.    
\   Read_FS_Cal ( -- )
\     - Reads the full scale calibration register from the a/d.
\   Read_Zero_Cal ( -- )
\     - Reads the zero scale calibration register from the a/d.
\   Buffer_On ( -- )
\     - Turns on the buffer for the AD7714 that allows the analog inputs
\       to handle higher source impedances.      
\   Buffer_Off ( -- )
\     - Turns off the buffer for the AD7714.     
\   Sync ( -- )
\     - Resets the modulator and digital filter without affecting any 
\       of the setup conditions on the part.   
\   Use_Onboard_Ref ( -- )                        
\     - Uses the on-board 2.5 volt reference as the reference voltage for the
\       analog to digital converter.
\   Use_External_Ref ( -- )
\     - Uses as external reference voltage as the reference voltage for the
\       analog to digital converter.
\   Start_Conversion ( cal_type\freq_int\gain\pol\word_length\bo\fsync\ch -- )
\     - Start a conversion with a calibration. 
\   Start_Conv_With_Values (fs_val\zero_val\freq_int\gain\pol\word\bo\fsync\ch -- )
\     - Start a coversion without a calibration. 
\   AD24_Sample ( timeout in timeslice counts -- a/d24 sample )
\     - Acquires one sample from the 24 bit A/D within the timeout period. 
\   AD24_Multiple ( num_samples\xaddr\timeout in timeslice counts-- success )
\     - Acquires num_samples from 24 bit A/D and stores it to xaddr within
\       the timeout period.
\ ---------------------------------------------------------------------
\ Notes: 
\        1.  The fastest sampling rate for a given first notch filter frequency
\            is the nyquist frequency:  Fnyquist = (1/2)*f*(1/(3*#channels))
\            #channels | Fnyquist for a first notch filter frequency of 60 Hz
\                 1    |  15. Hz or 15 samples per second max.
\                 2    |  05. Hz 
\                 3    |  3.3 Hz         
\                 4    |  2.5 Hz         
\                 5    |  2.0 Hz 
\            First Notch Filter Frequency = Sample Frequency
\        2.  10 Hz is the fastest first notch frequency that can be used if
\            50 & 60 Hz need to be filtered.  10 being the greatest common
\            factor of 50 & 60.
\        3.  2 additional channels are added to the 6 channels on the AD7714.
\            This is accomplished by multiplexing the two signals through the
\            analog switch.  Thus the channels are mapped as follows:
\            AD Module Channel   AD7714 Channel
\                    0                 1
\                    1                 2
\                    2                 1
\                    3                 2
\                    4                 3
\                    5                 4
\                    6                 5
\                    7                 6
\        4.  The interrupt service routine of AD24_Multiple runs at more than 
\            twice the frequency specified to the Start_Conversion or 
\            Start_Conv_With_Values routines.  This is done to eliminate
\            clock variations between the A/D and QED clocks and to gaurantee 
\            that a sample is not missed even if the ISR or SPI is delayed up to 1/2
\            a sample period or a full ISR period.  The equation used to calculate 
\            the sampling period is:
\  
\        Sampling Period = Floor (( A/D Period - INTERRUPT_LATENCY_DELAY ) / 2 )
\            where INTERRUPT_LATENCY_DELAY  = 260 us.
\ 
\            The INTERRUPT_LATENCY_DELAY is comprised of 200 us for the time to 
\            update the A/D data register with sample values, 10 us of interrupt 
\            latency delay, and 50 us to read the data ready line when the ISR is 
\            entered.  This equation can also used to caculate the maximum time 
\            this routine can be delayed or SPI used without missing a sample.  
\            For example to garauntee that a sample is not missed at the fastest 
\            sample rate of 1010.5 Hz, the max time this routine can be delayed:
\            0.0003648 = ((1/1010.5) - 0.00026) / 2 or 364.8 us.

